參數(shù)資料
型號: CDCL6010_07
廠商: Texas Instruments, Inc.
英文描述: 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer
中文描述: 1.8伏,11輸出時鐘倍頻,分銷商,抖動清除器和緩沖器
文件頁數(shù): 12/27頁
文件大?。?/td> 571K
代理商: CDCL6010_07
www.ti.com
SDA/SCL Bus Configuration Command Bitmap
Byte 0:
Byte 1:
Byte 2:
CDCL6010
SLLS780–FEBRUARY 2007
Word Write
Programming Sequence:
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
Data Byte High
A
P
Word Read
Programming Sequence:
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
Slave
Address
Command
Code
Slave
Address
S
Wr
A
A
S
Rd
A
Data Byte
A
Data Byte
N
P
Power Up
Condition
0
Bit
7
6
5
4
3
2
1
0
Bit Name
PLL-LOCK
MANF[6]
MANF[5]
MANF[4]
MANF[3]
MANF[2]
MANF[1]
MANF[0]
Description/Function
Type
R
R
R
R
R
R
R
R
Reference To
1 if PLL has achieved lock, otherwise 0
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Power Up
Condition
0
0
1
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Bit Name
RES
RES
ENPH
PH1[4]
PH1[3]
PH1[2]
PH1[1]
PH1[0]
Description/Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reference To
Reserved
Reserved
Phase select enable
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Table 4
,
Table 5
Table 4
,
Table 5
Table 4
,
Table 5
Table 4
,
Table 5
Table 4
,
Table 5
Power Up
Condition
0
0
1
0
Bit
7
6
5
4
Bit Name
RES
RES
ENP1
ENBP1
Description/Function
Type
R/W
R/W
R/W
R/W
Reference To
Reserved
Reserved
Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled
Bypass PLL for post-divider P1: If 1 input is CLKP/CLKN, if 0 input is PLL
clock
Divide ratio select for post-divider P1
Divide ratio select for post-divider P1
Divide ratio select for post-divider P1
Divide ratio select for post-divider P1
3
2
1
0
SELP1[3]
SELP1[2]
SELP1[1]
SELP1[0]
R/W
R/W
R/W
R/W
0
1
1
1
Table 1
Table 1
Table 1
Table 1
12
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