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參數(shù)資料
| 型號： | CDCDLP223_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3 V Clock Synthesizer for DLP Systems |
| 中文描述： | 3.3伏時(shí)鐘合成器的投影系統(tǒng) |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 189K |
| 代理商： | CDCDLP223_07 |
www.ti.com
TIMING REQUIREMENTS
(1)
over recommended ranges of supply voltage, load and operating free air temperature
CDCDLP223
SCAS836–DECEMBER 2006
PARAMETER
MIN
TYP
MAX
UNIT
XIN, XOUT REQUIREMENTS
f
XIN
Frequency of crystal attached to XIN, XOUT, with C
L
= 20 pF (2
×
40 pF) on-die
capacitance
2 WIRE SERIAL INTERFACE REQUIREMENTS STANDARD MODE
f
SCLK
SCLK frequency
t
h(START)
START hold time (see
Figure 1
)
t
w(SCLL)
SCLK low-pulse duration (see
Figure 1
)
t
w(SCLH)
SCLK high-pulse duration (see
Figure 1
)
t
su(START)
START setup time (see
Figure 1
)
t
h(SDATA)
SDATA hold time (see
Figure 1
)
t
su(SDATA)
SDATA setup time (see
Figure 1
)
t
r(SDATA)
SCLK / SDATA input rise time (see
Figure 1
)
t
f(SDATA)
SCLK / SDATA input fall time (see
Figure 1
)
t
su(STOP)
STOP setup time (see
Figure 1
)
t
BUS
Bus free time
2 WIRE SERIAL INTERFACE REQUIREMENTS FAST MODE
f
SCLK
SCLK frequency
t
h(START)
START hold time (see
Figure 1
)
t
w(SCLL)
SCLK low-pulse duration (see
Figure 1
)
t
w(SCLH)
SCLK high-pulse duration (see
Figure 1
)
t
su(START)
START setup time (see
Figure 1
)
t
h(SDATA)
SDATA hold time (see
Figure 1
)
t
su(DATA)
SDATA setup time (see
Figure 1
)
t
r(SDATA)
SCLK / SDATA input rise time (see
Figure 1
)
t
f(SDATA)
SCLK / SDATA input fall time (see
Figure 1
)
t
su(STOP)
STOP setup time (see
Figure 1
)
t
BUS
Bus free time
20
MHz
0
100
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
μ
s
4.0
4.7
4.0
4.7
0
3.45
250
1000
300
4.0
4.7
0
400
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
μ
s
0.6
1.3
0.6
0.6
0
0.9
100
20
20
0.6
1.3
300
300
(1)
The CDCDLP223 2-wire serial interface in Send-Mode meets both I
2
C and SMBus
set up time
t
su
and
hold time
t
h
requirements.
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCDLP223PW | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWRG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCE18005 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Five/Ten Output Clock Generator/Buffer |
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