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參數(shù)資料
| 型號： | CDCDLP223_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3 V Clock Synthesizer for DLP Systems |
| 中文描述： | 3.3伏時鐘合成器的投影系統(tǒng) |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 189K |
| 代理商： | CDCDLP223_07 |
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
RECOMMENDED OPERATING CONDITIONS
RECOMMENDED CRYSTAL SPECIFICATION
(1)
CDCDLP223
SCAS836–DECEMBER 2006
VALUE
–0.5 to 4.6
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
±
20
±
17.5
–65 to 150
UNIT
V
V
V
mA
mA
°
C
V
DD
V
I
V
O
Supply voltage range
Input voltage range
(2)
Output voltage range
(2)
Input current (V
I
< 0, V
I
> V
DD
)
Continuous output current
Storage temperature range
I
O
Tstg
(1)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(2)
PACKAGE THERMAL IMPEDANCE FOR TSSOP20 PACKAGE
(1)
Airflow (lfm)
0
150
250
500
θ
JA
(
°
C/W)
83.0
77.9
75.4
71.4
θ
JC
(
°
C/W)
32
–
–
–
θ
JB
(
°
C/W)
54
–
–
–
Ψ
JT
(
°
C/W)
0.25
(1)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k
board).
MIN
-40
3.0
NOM
MAX
UNIT
°
C
V
V
T
A
V
DD
V
IH
Operating free-air temperature
Supply voltage
High level input voltage SDATA and SCLK
85
3.6
V
DD
0.3
×
V
DD
0.8
3.3
0.7
×
V
DD
–0.15
V
IL
Low level input voltage SDATA and SCLK
V
V
IL
V
I
V
IH
I
OH
I
OL
I
OH
I
OL
t
PU
Low level input voltage LVTTL
thresh Input Voltage threshold LVTTL
High level input voltage LVTTL
High-level output current LVTTL
Low-level output current LVTTL
High-level output current HCLK/HCLK
Low-level output current HCLK/HCLK
Power-up time for all VDDs to reach minimum specified voltage (power ramps must be
monotonic)
V
V
V
1.40
2.0
–8
8
mA
mA
mA
mA
ms
–20
0
0.05
500
MIN
NOM
MAX
UNIT
MHz
μ
W
pF
f
xtal
ESR
P
drive
C
L
Crystal input frequency (fundamental)
Effective series resistance
Maximum power handling (drive level)
Load capacitance
20
100
100
20
(1)
See DLP Control ASIC DDP2230 datasheet for additional requirements.
3
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDCDLP223PW | 功能描述:時鐘合成器/抖動清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWG4 | 功能描述:時鐘合成器/抖動清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWR | 功能描述:時鐘合成器/抖動清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWRG4 | 功能描述:時鐘合成器/抖動清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCE18005 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Five/Ten Output Clock Generator/Buffer |
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