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參數(shù)資料
| 型號(hào)： | CDCDLP223_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3 V Clock Synthesizer for DLP Systems |
| 中文描述： | 3.3伏時(shí)鐘合成器的投影系統(tǒng) |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 189K |
| 代理商： | CDCDLP223_07 |
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
XIN
100 Mhz
300 Mhz
20 Mhz
VSS
VDD
SSC PLL 1
OUT = 100 Mhz
–0.5% SSC
2-Wire Serial
Interface
Control
Logic
LVTTL
Crystal
Oscillator
20 Mhz
XOUT
SCLK
SDATA
IREF
IDO
EN
VDD
HCLK out
HCLK out
SSC PLL 2
OUT = 200-400 Mhz
±1.0% and
±1.5% SSC
150 K
W
VDD
150 K
W
CDCDLP223
SCAS836–DECEMBER 2006
TERMINAL FUNCTIONS
TERMINAL
XIN
XOUT
SDATA
SCLK
20 MHz
100 MHz
100 MHz
300 MHz
300 MHz
VDD
VSS
IREF
PIN
1
2
9
10
5
18
17
14
13
TYPE
I
O
DESCRIPTION
Crystal oscillator input for 20-MHz crystal in parallel resonance
Crystal oscillator output for 20-MHz crystal in parallel resonance
Data I/O, 2-wire serial interface controller, internal 1-M
pullup
I Interface Clock Clock input, 2-wire serial interface controller, internal 1-M
pullup
O LVTTL
Clock output, 20 MHz (buffered output from crystal oscillator)
O HCLK
Clock output for XDR clock generator
O HCLK
Clock output for XDR clock generator
O HCLK
Clock output for DMD system
O HCLK
Clock output for DMD system
Power
3.3 V Power supply
Ground
Ground
O R
REF
to GND
IREF pin for HCLK output drive-current biasing
Output enable, 20 MHz, 100 MHz and 200–400 MHz outputs, 150 k
pullup, default =
I LVTTL
logic high
Sets 2-wire serial interface ID address bit A0, 150 k
pull-up resistor, default = logic
I LVTTL
high
I/O Open drain
4,11,19
3,6,12,15,16
20
EN
7
IDO
8
Table 1. EN Pin (20 MHz, 100 MHz and 300 MHz Clocks)
EN PIN
1
DESCRIPTION
All HCLK outputs, and 20-MHz outputs enabled, detailed device configurations are determined by 2-wire serial interface
settings.
All HCLK = true Hi-Z, both PLLs are powered down and 20-MHz output in Hi-Z and Crystal Oscillator disabled, EN overrides
2-wire serial interface settings.
0
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCDLP223PW | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCDLP223PWRG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Clock Synth for DLP Systems RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCE18005 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Five/Ten Output Clock Generator/Buffer |
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