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參數(shù)資料
| 型號： | CDC9843DW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| 中文描述： | PC主板時(shí)鐘合成器/ 3驅(qū)動態(tài)輸出 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CDC9843DW |
CDC9843
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS559C – DECEMBER 1995 – REVISED OCTOBER 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
Duty Cycle
VOLTAGE WAVEFORMS
tr
tf
tc
2.4 V
1.5 V
0.4 V
LOAD CIRCUIT
From Output
Under Test
CL = 20 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
tf
≤
2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
10 MHz, ZO = 50
, tr
≤
2.5 ns,
Figure 1. Load Circuit and Voltage Waveforms
HCLK-to-HCLK Skew
Skew
1.5 V
1.5 V
VOH
GND
VOH
GND
CPU Clock
(HCLK)
CPU Clock
(HCLK)
PCLK-to-PCLK Skew
Skew
1.5 V
1.5 V
VOH
GND
VOH
GND
PCI Clock
(PCLK)
PCI Clock
(PCLK)
Offset
1.5 V
1.5 V
VOH
GND
CPU Clock
(HCLK)
PCI Clock
(PCLK)
VOH
GND
Offset
HCLK-to-PCLK Offset
Figure 2. Waveforms for Calculation of t
Skew
and t
offset
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