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參數(shù)資料
| 型號： | CDC9843DW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| 中文描述： | PC主板時鐘合成器/ 3驅(qū)動態(tài)輸出 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CDC9843DW |
CDC9843
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS559C – DECEMBER 1995 – REVISED OCTOBER 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
5
UNIT
After SEL1, SEL0
After OE
↑
After power up
Stabilization time
5
5
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
switching characteristics (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.135 V
to 3.6 V,
TA = 0
°
C to 70
°
C
MIN
UNIT
MAX
tSkew
HCLKn
200
ps
PCLKn
400
ps
Offset
HCLKn
PCLKn
1
4
ns
Jitter
HCKLn
±
250
±
350
ps
PCKLn
ps
Duty cycle
Any output
45%
55%
SEL0 = L, SEL1 = L
SEL0 = L, SEL1 = H
20
ns
ns
HCKLn
16.7
t
tc
SEL0 = H, SEL1 = L
15
ns
SEL0 = L, SEL1 = L
40
ns
PCLKn
SEL0 = L, SEL1 = H
33.3
ns
SEL0 = H, SEL1 = L
30
ns
t§
tr§
HCLKn
2
ns
PCKLn
t§
tf§
HCKLn
2
ns
PCLKn
Specifications are applicable only after the PLL stabilization time has elapsed.
§Rise and fall times are characterized using the load circuits shown in Figure 1.
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