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參數(shù)資料
| 型號： | CDC9843DW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| 中文描述： | PC主板時鐘合成器/ 3驅動態(tài)輸出 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CDC9843DW |
CDC9843
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS559C – DECEMBER 1995 – REVISED OCTOBER 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
OE
SEL0
SEL1
X1
HCLKn
PCLKn
REFn
SBCLK
FCCLK
L
X
X
14.318 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
L
L
14.318 MHz
50 MHz
25 MHz
14.318 MHz
48 MHz
24 MHz
H
L
H
14.318 MHz
60 MHz
30 MHz
14.318 MHz
48 MHz
24 MHz
H
H
L
14.318 MHz
TCLK
66 MHz
33 MHz
14.318 MHz
48 MHz
24 MHz
H
H
H
TCLK/2
TCLK/4
TCLK
TCLK/4
TCLK/8
TCLK is a test-clock input at the X1 input during test mode.
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