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參數(shù)資料
| 型號(hào)： | CDC9162 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時(shí)鐘合成器/驅(qū)動(dòng)器(三態(tài)輸出)) |
| 中文描述： | 電腦主板時(shí)鐘Sythesizer /支持與SDRAM時(shí)鐘驅(qū)動(dòng)器（電腦母板時(shí)鐘合成器/驅(qū)動(dòng)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 211K |
| 代理商： | CDC9162 |
CDC9162
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS573 – JUNE 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
Duty Cycle
From Output
Under Test
CL
(see Note A)
2.5-V CLOCK WAVEFORMS
tr
tf
t(L)
tc
2.0 V
1.25 V
0.4 V
tP
t(H)
Duty Cycle
3.3-V CLOCK WAVEFORMS
tr
tf
t(L)
tc
2.4 V
1.5 V
0.4 V
tP
t(H)
NOTES: A. CL includes probe and jig capacitance.
– CL = 30pF for PCLK0–PCLK7
– CL = 45pF for REF0
– CL = 20pF for all other outputs
B. All input pulses are supplied by generators having the following characteristics: PRR
tf
≤
2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
10 MHz, ZO = 50
, tr
≤
2.5 ns,
Figure 1. Load Circuit and Voltage Waveforms
P
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