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參數(shù)資料
| 型號(hào)： | CDC857-3DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS |
| 中文描述： | 2.5-/3.3-V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 157K |
| 代理商： | CDC857-3DGG |
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges or supply voltage and operating free–air
temperature
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
fC
Clock frequency
66
167
MHz
Input clock duty cycle
Stabilization time
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed–frequency, fixed–phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay,
skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation
under SSC application.
40%
60%
0.1
ms
switching characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tPLH
Low–to high level propagation delay time
(see Figure 5)
CLK mode/CLK to any output
1.5
3.5
6
ns
tPHL
High–to low level propagation delay time
(see Figure 5)
CLK mode/CLK to any output
1.5
3.5
6
ns
ten
tdis
Output enable time
CLK mode/G to any Y output
3
ns
Output disable time
CLK mode/G to any Y output
3
ns
t(jitt )
t(jitter)
Jitter (peak to peak)
Jitter (peak-to–peak)
66 MHz
120
ps
100/125/133/167 MHz
75
t(jitt )
t(jitter)
Jitter (cycle to cycle)
Jitter (cycle-to-cycle)
66 MHz
110
ps
100/125/133/167 MHz
65
t(phase error)
tskew(0)
tskew(p)
Phase error (see Figure 4)
All differential input and output termi-
All differential in ut and out ut termi-
nals are terminated with 120
/
16 F
i Fi
16 pF as shown in Figure 2
–150
150
ps
Output skew (see Figure 4)
100
ps
Pulse skew
100
ps
Duty cycle§(see Figure 6)
Duty cycle§ (see Figure 6)
66 MHz to 100 MHz
49.5%
50.5%
101 MHz to 167 MHz
Load = 120
/16 pF
49%
51%
tr, tf
Refers to transition of noninverting output.
§While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty
cycle = twH/tc, were the cycle time (tc) decreases as the frequency goes up.
Output rise and fall times (20% – 80%)
650
800
950
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CDC857-3DGGG4 | 功能描述:鎖相環(huán) - PLL Phase-Lock Loop Clock Drivers RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CDC857-3DGGR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDC906 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER |
| CDC906PW | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Custom Prog 3-PLL Clock RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC906PWG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Custom Prog 3-PLL Clock RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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