- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379831 > CDC857-3DGG (Texas Instruments, Inc.) 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS PDF資料下載
參數(shù)資料
| 型號： | CDC857-3DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS |
| 中文描述： | 2.5-/3.3-V鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 157K |
| 代理商： | CDC857-3DGG |
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SPECIAL TEST MODES
INPUTS
OUTPUTS
COMMENTS
VCC
ON
AVCC
0 V
G
L
CLK
L
Y
Z
Y
Z
FBOUT
Z
FBOUT
Z
Clock Mode
ON
0 V
L
H
Z
Z
Z
Z
Clock Mode
ON
0 V
H
L
L
H
L
H
Clock Mode
ON
0 V
UP
UP
H
↓
§
↓
§
H
H
L
H
L
Clock Mode
ON
L
Z
Z
L
H
PLL Mode
ON
H
Z
Z
H
L
PLL Mode
Only one signal shown for this differential input.
AVCC ramped up after two (2) high-to-low transitions on G input & G being low.
§At least two (2) high-to-low transitions during AVCC = 0.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
NO.
17
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
AVCC
16
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down.
CLK
CLK
13
14
I
Clock input, CLK provides the clock signal to be distributed by the CDC857 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
FBIN
FBIN
36
35
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired
to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBOUT
FBOUT
32
33
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
G
37
I
Output bank enable. G is the output enable for outputs Y and Y. When G is low outputs Y are disabled
to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same
frequency as CLK.
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
Ground
VCC
4, 11, 12,
15, 21, 28,
34, 38, 45
Power
Power supply
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
3, 5, 10,
20, 22, 46,
44, 39, 29,
27
O
Clock outputs. These outputs provide low-skew copies of CLK.
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
2, 6, 9,
19, 23, 47,
43, 40, 30,
26
O
Clock outputs. These outputs provide low-skew copies of CLK.
相關PDF資料 |
PDF描述 |
|---|---|
| CDC913DB | PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS |
| CDC913DW | PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS |
| CDC913 | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時鐘發(fā)生器(帶雙1-4緩沖器和三態(tài)輸出)) |
| CDC9161 | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時鐘合成器/驅(qū)動器(三態(tài)輸出)) |
| CDC9162 | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時鐘合成器/驅(qū)動器(三態(tài)輸出)) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDC857-3DGGG4 | 功能描述:鎖相環(huán) - PLL Phase-Lock Loop Clock Drivers RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CDC857-3DGGR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDC906 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER |
| CDC906PW | 功能描述:時鐘合成器/抖動清除器 Custom Prog 3-PLL Clock RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC906PWG4 | 功能描述:時鐘合成器/抖動清除器 Custom Prog 3-PLL Clock RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。