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參數(shù)資料
| 型號(hào)： | CDC338 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Phase-lock Loop Clock Driver with 3 state Output(鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器(三態(tài)輸出)) |
| 中文描述： | 鎖相3態(tài)輸出環(huán)路時(shí)鐘驅(qū)動(dòng)器（鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 153K |
| 代理商： | CDC338 |
CDC338
PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS418 – MAY 1992 – REVISED FEBRUARY 1993
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 3)
MIN
MAX
UNIT
fclock
tw
Clock frequency
15
35
MHz
Pulse duration
CLR low
5
ns
Input clock duty cycle
40%
60%
S bili
Stabilization time
After CLR
↓
After OE
↓
After power up
50
tstabilize
50
50
s
μ
NOTE 3: Preliminary specifications based on SPICE analysis.
Time required for the integrated phase-lock loop circuits to obtain phase-lock of their feedback signals to their reference signals. In order for phase
lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (see Note 4 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
fmax
tPLH
tPHL
tsk(o)
DC
35
MHz
CLKIN
↑
DF, HF, or Y
±
1
±
1
0.5
ns
HF
CLKIN
DF, HF, or Y
ns
DF, HF, or Y
45%
55%
tr
tf
ns
ns
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
P
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