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| 型號(hào)： | CDC2509PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3 - V相位鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | CDC2509PW |
CDC2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS580A – OCTOBER 1996 – REVISED JANUARY 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclock
Clock frequency
25
125
MHz
Input clock duty cycle
Stabilization time
40%
60%
1
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Note 5 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.165 V
VCC = 3.3 V
±
0.3 V
MIN
TYP
MAX
MIN
TYP
MAX
tphase error,
reference
(see Figure 3)
66 MHz < CLKIN
↑
< 100 MHz
FBIN
↑
–0.7...0.1
ns
tphase error,
– jitter
(see Note 6)
tsk(o)§
Jitter(pk-pk)
Duty cycle
reference
(see Figure 4)
CLKIN
↑
= 100 MHz
FBIN
↑
–500
–50
–310
ps
Any Y or FBOUT
Any Y or FBOUT
200
ps
Any Y or FBOUT
–100
100
ps
F(clkin
≤
66 MHz)
Any Y or FBOUT
45%
55%
F(clkin > 66 MHz)
Any Y or FBOUT
43%
55%
tr
tf
Any Y or FBOUT
1.3
1.9
0.8
2.1
ns
Any Y or FBOUT
1.7
2.3
1.2
2.5
ns
These parameters are not production tested.
§The tsk(o) specification is only valid for equal loading of all outputs.
NOTES:
5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is –600 ps to 50 ps for the 5% VCC range.
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| CDC2509PWLE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Nine Distributed-Output Clock Driver |
| CDC2509PWR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2509PWRG4 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2510 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| CDC2510A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3-V Phase-Lock Loop Clock Driver |
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