參數(shù)資料
型號: CDB4271
廠商: Cirrus Logic Inc
文件頁數(shù): 21/29頁
文件大?。?/td> 0K
描述: EVAL BOARD CS4271 STEREO CODEC
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻編解碼器
嵌入式: 是,F(xiàn)PGA / CPLD
已用 IC / 零件: CS4271
主要屬性: 立體聲 24 位 192 kHz 采樣率
次要屬性: I²S,S/PDIF 輸入和輸出,模擬輸入和輸出,GUI
已供物品: 板,纜線,CD
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS4271-DZZR-ND - IC CODEC 24BIT 114DB 28-TSSOP
CS4271-DZZ-ND - IC CODEC 24BIT 114DB 28-TSSOP
598-1041-5-ND - IC CODEC AUD 24BIT 114DB 28TSSOP
其它名稱: 598-1003
CS4271
28
DS592F1
To operate the CS4271 with an externally generated MCLK signal, no crystal should be used, XTI should be con-
nected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven
externally with an appropriate speed clock.
5.2.3.2
Clock Ratio Selection
Depending on the use of an external crystal, or whether the CS4271 is in Master or Slave Mode, different
MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control Port Register Bits that must
be set in order to obtain them are shown in Tables 8 and 9 below.
Notes: 25. For the Ratio1 and Ratio0 bits listed above, “d” indicates that any value may written.
Table 7. Crystal Frequencies
Mode
Crystal Frequency
Single Speed
512 x Fs
Double Speed
256 x Fs
Quad Speed
128 x Fs
Table 8. Clock Ratios - Control Port Mode With External Crystal
External Crystal Used, MCLK=Output
Master Mode
MCLK/LRCK
SCLK/LRCK
LRCK
Ratio1 Bit
Ratio0 Bit
Single Speed
256
64
Fs
0
512
64
Fs
1
Double Speed
128
64
Fs
0
256
64
Fs
1
Quad Speed
128
64
Fs
Slave Mode
MCLK/LRCK
SCLK/LRCK
LRCK
Ratio1 Bit
Ratio0 Bit
Single Speed
256
32, 64, 128
Fs
0
512
32, 64, 128
Fs
1
Double Speed
128
32, 64
Fs
0
256
32, 64
Fs
1
Quad Speed
128
32, 64
Fs
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