
CS4271
22
DS592F1
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: logic 0 = AGND, logic 1 = VL)
Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For FSCK < 1 MHz
Parameter
Symbol
Min
Max
Unit
SPI Mode
CCLK Clock Frequency.
fsclk
-6
MHz
RST Rising Edge to CS Falling.
tsrs
500
-
ns
CCLK Edge to CS Falling.
tspi
500
-
ns
CS High Time Between Transmissions.
tcsh
1.0
-
s
CS Falling to CCLK Edge.
tcss
20
-
ns
CCLK Low Time.
tscl
82
-
ns
CCLK High Time.
tsch
82
-
ns
CDIN to CCLK Rising Setup Time.
tdsu
40
-
ns
CCLK Rising to DATA Hold Time.
tdh
15
-
ns
Rise Time of CCLK and CDIN.
tr2
-100
ns
Fall Time of CCLK and CDIN.
tf2
-100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
Figure 7. SPI Control Port Timing