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參數資料
| 型號： | CD74FCT654M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | FCT Interface Logic, Octal Bus Transceivers/ Registers, Open Drain (A Side), Three-State (B Side) |
| 中文描述： | 聯邦首都接口邏輯，八路總線收發(fā)器/寄存器，開漏（阿方），三態(tài)（乙方） |
| 文件頁數： | 6/9頁 |
| 文件大?。?/td> | 49K |
| 代理商： | CD74FCT654M |
8-6
Switching Specifications Over Operating Range
t
r
, t
f
= 2.5ns, C
L
= 50pF, R
L
(Figures 3, 4)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
0
o
C TO 70
o
C
UNITS
TYP
MIN
MAX
Propagation Delays
Stored An
→
Bn
CD74FCT653
t
PLH
, t
PHL
5
6.8
2
9
ns
Stored An
→
Bn
CD74FCT654
t
PLH
, t
PHL
5
6.8
2
9
ns
Stored Bn
→
An
CD74FCT653
t
PZL
5
6
2
8
ns
t
PLZ
5
6.8
2
9
ns
Stored Bn
→
An
CD74FCT654
t
PZL
, t
PLZ
5
6.8
2
9
ns
An
→
Bn
CD74FCT653
t
PLH
, t
PHL
5
6
2
8
ns
An
→
Bn
CD74FCT654
t
PLH
, t
PHL
5
6.8
2
9
ns
Bn
→
An
CD74FCT653
t
PZL
5
6
2
8
ns
t
PLZ
5
6.8
2
9
ns
Bn
→
An
CD74FCT654
t
PZL
, t
PLZ
5
6.8
2
9
ns
Select to Data (B Bus)
CD74FCT653,
CD74FCT654
t
PLH
, t
PHL
5
8.3
2
11
ns
Select to Data (A Bus)
CD74FCT653
t
PZL
5
6
2
8
ns
t
PLZ
5
6.8
2
9
ns
Select to Data (A Bus)
CD74FCT654
t
PZL
, t
PLZ
5
6.8
2
9
ns
Three-State Enabling Times (B Bus),
Bus to Output or Register to Output
CD74FCT653
t
PZL
, t
PZH
5
10.5
2
14
ns
CD74FCT654
t
PZL
, t
PZH
5
11.3
2
15
ns
Three-State Disabling Time (B Bus),
Bus to Output or Register to Output
CD74FCT653
t
PLZ
, t
PZH
5
6.8
2
9
ns
CD74FCT654
t
PLZ
, t
PZH
5
6.8
2
9
ns
Off State Enabling Times (A Bus),
Bus to Output or Register to Output
CD74FCT653
t
PZL
5
10.5
2
14
ns
CD74FCT654
t
PZL
5
11.3
2
15
ns
Off State Disabling Time (A Bus),
Bus to Output or Register to Output
CD74FCT653
t
PLZ
5
6.8
2
9
ns
CD74FCT654
t
PLZ
5
6.8
2
9
ns
Prerequisite for Switching
t
r
, t
f
= 2.5ns, C
L
= 50pF, R
L
(Figures 3, 4)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
0
o
C TO 70
o
C
UNITS
TYP
MIN
MAX
Maximum Frequency (B Side as Outputs)
f
MAX
5
(Note 8)
-
80
-
MHz
Data to Clock Setup Time
t
SU
5
-
4
-
ns
Data to Clock Hold Time
t
H
5
-
2
-
ns
Clock Pulse Width
t
W
5
-
6
-
ns
CD74FCT653, CD74FCT654
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