參數(shù)資料
型號(hào)： CD4034BMS
廠商： Intersil Corporation
英文描述： CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register(CMOS 8級(jí) 靜態(tài)雙向串/并輸入/輸出總線寄存器)
中文描述： 的CMOS 8級(jí)靜態(tài)雙向并行/串行輸入/輸出總線寄存器（的CMOS 8級(jí)靜態(tài)雙向串/并輸入/輸出總線寄存器）
文件頁數(shù)： 5/14頁
文件大小： 147K
代理商： CD4034BMS
7-841
Specifications CD4034BMS
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
-
-2.4
mA
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
+7
-
V
Propagation Delay
Parallel In to Parallel Out
TPHL
TPLH
VDD = 10V
1, 2, 3
-
240
ns
VDD = 15V
1, 2, 3
-
170
ns
Propagation Delay
Serial to Parallel Out
TPHL
TPLH
VDD = 5V
1, 2, 3
700
-
ns
VDD = 10V
1, 2, 3
-
240
ns
VDD = 15V
1, 2, 3
-
170
ns
Propagation Delay 3-State
AE to Out ‘A’
TPLZ
TPHZ
VDD = 10V
1, 2, 3, 4
-
160
ns
VDD = 15V
1, 2, 3, 4
-
120
ns
Propagation Delay 3-State
AE to Out ‘A’
TPZL
TPZH
VDD = 10V
1, 2, 3, 4
-
160
ns
VDD = 15V
1, 2, 3, 4
-
120
ns
Transition Time
TTLH
TTHL
VDD = 10V
1, 2, 3
-
100
ns
VDD = 15V
1, 2, 3
-
80
ns
Maximum Clock Input
Frequency
FCL
VDD = 10V
1, 2, 3
5
-
MHz
VDD = 15V
1, 2, 3
7
-
MHz
Minimum Data Setup
Time
Serial Data to Clock
TS
VDD = 5V
1, 2, 3
-
160
ns
VDD = 10V
1, 2, 3
-
60
ns
VDD = 15V
1, 2, 3
-
40
ns
Minimum Data Setup
Time Parallel Data to
Clock
TS
VDD = 5V
1, 2, 3
-
50
ns
VDD = 10V
1, 2, 3
-
30
ns
VDD = 15V
1, 2, 3
-
20
ns
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
-
250
ns
VDD = 10V
1, 2, 3
-
100
ns
VDD = 15V
1, 2, 3
-
70
ns
Maximum Clock Rise and
Fall Time (Note 5)
TRCL
TFCL
VDD = 5V
1, 2, 3
-
15
μ
s
VDD = 10V
1, 2, 3
-
15
μ
s
VDD = 15V
1, 2, 3
-
15
μ
s
Minimum High Level
Pulse Width AE, P/S, A/S
TW
VDD = 5V
1, 2, 3
-
350
ns
VDD = 10V
1, 2, 3
-
140
ns
VDD = 15V
1, 2, 3
-
80
ns
Input Capacitance
CIN
Any Input
1, 2
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
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