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參數(shù)資料
| 型號(hào)： | CD4034BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register(CMOS 8級(jí) 靜態(tài)雙向串/并輸入/輸出總線寄存器) |
| 中文描述： | 的CMOS 8級(jí)靜態(tài)雙向并行/串行輸入/輸出總線寄存器（的CMOS 8級(jí)靜態(tài)雙向串/并輸入/輸出總線寄存器） |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 147K |
| 代理商： | CD4034BMS |
7-847
CD4034BMS
FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES)
TRUTH TABLE REGISTER INPUT-LEVELS AND
RESULTING REGISTER OPERATION
“A”
ENABLE
P/S
A/B
A/S
OPERATION*
0
0
0
X
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled
0
0
1
X
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
0
1
0
0
Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
0
1
0
1
Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
0
1
1
0
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Synch. Data
Recirculation
0
1
1
1
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Asynch. Data
Recirculation
1
0
0
X
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
1
0
1
X
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
1
1
0
0
Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output
1
1
0
1
Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output
1
1
1
0
Parallel Mode; “A” Synch, Parallel Data Input, “B” Parallel Data Output
1
1
1
1
Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output
*Outputs change at positive transition of clock in the serial mode and when the A/S control input is “l(fā)ow” in the parallel mode. During
transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops.
1 = High Level
0 = Low Level
X = Don’t Care
CLS
CLS
p
n
CLS
CLS
p
n
CLM
CLM
p
n
CLM
CLM
p
n
P/S
P/S
p
n
K
K
p
n
L
L
p
n
Bn
VDD
VDD
VSS
VSS
Q’
M
Q’
M
N
Q’
N
1 OF 8 STAGES
SERIAL
DATA
D
VSS
VDD
VSS
PROTECTION NETWORK
ON ALL “A” AND “B”
DATA INPUTS
PROTECTION NETWORK
ON SERIAL DATA INPUT
An
Q (TO NEXT STAGE D)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD4035BMS | CMOS 4 -Stage Parallel In/Parallel Out Shift Register(CMOS 4級(jí)并入并出移位寄存器) |
| CD4035 | Replaced by ISO124 : Low Cost, High Voltage, Wide Bandwidth Standard Hermetic DIP Signal Isolation Buffer Amplifiers 16-CDIP SB |
| CD4035 | 4-Bit Parallel-In/Parallel-Out Shift Register |
| CD4035BC | Replaced by ISO124 : |
| CD4035BM | 4-Bit Parallel-In/Parallel-Out Shift Register |
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參數(shù)描述 |
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| CD4034BNSR | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BNSRE4 | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BNSRG4 | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BPW | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BPWE4 | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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