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參數(shù)資料
| 型號(hào)： | CD4034BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register(CMOS 8級(jí) 靜態(tài)雙向串/并輸入/輸出總線寄存器) |
| 中文描述： | 的CMOS 8級(jí)靜態(tài)雙向并行/串行輸入/輸出總線寄存器（的CMOS 8級(jí)靜態(tài)雙向串/并輸入/輸出總線寄存器） |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大小： | 147K |
| 代理商： | CD4034BMS |
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7-838
CD4034BMS
Parallel Operation
A high P/S input signal allows data transfer into the register
via the parallel data lines synchronously with the positive
transition of the clock provided the A/S input is low. If the A/S
input is high the transfer is independent of the clock. The
direction of data flow is controlled by the A/B input. When
this signal is high the A data lines are inputs (and B data
lines are outputs); a low A/B signal reverses the direction of
data flow.
The AE input is an additional feature which allows many reg-
isters to feed data to a common bus. The A DATA lines are
enabled only when this signal is high.
Data storage through recirculation of data in each register
stage is accomplished by making the A/B signal high and the
AE signal low.
Serial Operation
A low P/S signal allows serial data to transfer into the regis-
ter synchronously with the positive transition of the clock.
The A/S input is internally disabled when the register is in
the serial mode (asynchronous serial operation is not
allowed).
The serial data appears as output data on either the B lines
(when A/B is high) or the A lines (when A/B is low and the
AE signal is high).
Register expansion can be accomplished by simply cascad-
ing CD4034BMS packages.
The CD4034BMS is supplied in these 24 lead outline pack-
ages:
Braze Seal DIP
Ceramic Flatpack
H4V
H4P
Functional Diagram
SI
STEERING
LOGIC
SI
Q
A1
B1
SI
6
STAGES
Q
A8
B8
SI
A
B
AE
A/B
A/S
P/S
CL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD4035BMS | CMOS 4 -Stage Parallel In/Parallel Out Shift Register(CMOS 4級(jí)并入并出移位寄存器) |
| CD4035 | Replaced by ISO124 : Low Cost, High Voltage, Wide Bandwidth Standard Hermetic DIP Signal Isolation Buffer Amplifiers 16-CDIP SB |
| CD4035 | 4-Bit Parallel-In/Parallel-Out Shift Register |
| CD4035BC | Replaced by ISO124 : |
| CD4035BM | 4-Bit Parallel-In/Parallel-Out Shift Register |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4034BNSR | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BNSRE4 | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BNSRG4 | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BPW | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4034BPWE4 | 功能描述:計(jì)數(shù)器移位寄存器 CMOS 8-St Static Bi Para/Ser Input RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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