參數(shù)資料
型號: CD4029BMS
廠商: Intersil Corporation
元件分類: 通用總線功能
英文描述: CMOS Presettable Up/Down Counter(CMOS可預置加/減計數(shù)器)
中文描述: 的CMOS可預置加/減計數(shù)器的CMOS(可預置加/減計數(shù)器)
文件頁數(shù): 9/11頁
文件大?。?/td> 124K
代理商: CD4029BMS
7-806
CD4029BMS
Typical Performance Characteristics
(Continued)
Timing Diagrams
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (CARRY
OUTPUT)
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION
OF FREQUENCY
AMBIENT TEMPERATURE (T
A
) = +25
o
C
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
P
P
,
P
)
300
200
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
1
10
CLOCKFREQUENCY (fCL) (kHz)
10
2
10
3
10
4
2
4 6 8
2
4 6 8
2
4 6 8
2
4 6 8
2
4
6
8
10
10
3
10
4
10
5
10
2
P
μ
W
2
4 6 8
2
4
6
8
2
4
6
8
2
4
6
8
CL = 50pF
CL = 15pF
SUPPLY VOLTAGE (VDD) = 15V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
10V
10V
5V
CARRY IN
(CL ENABLE)
UP/DOWN
BINARY/
DECADE
PRESET
ENABLE
J1
J2
J3
J4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT
5
6
7
8
9 10 11 12 13 14 15 9
8
7
6
5
4
3
2
1
0
0
15
CLOCK (CL)
The CD4029BMS CLOCK and UP/DOWN inputs are used
directly in most applications. In applications where CLOCK
UP and CLOCK DOWN inputs are provided, conversion to
the CD4029BMS CLOCK and UP/DOWN inputs can easily
be realized by use of the circuit in Figure 11.
CD4029BMS changes count on positive transitions of
CLOCK UP or CLOCK DOWN inputs. For the gate configu-
ration in Figure 12, when counting up the CLOCK DOWN
input must be maintained high and conversely when count-
ing down the CLOCK UP input must be maintained high.
FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN
INPUT SIGNALS TO CLOCK AND UP/DOWN
INPUT SIGNALS
“UP/DOWN”
“CLOCK”
VDD
1 CD4011
QUAD 2 INPUT NAND GATE
“CLOCK UP”
“CLOCK
DOWN”
相關PDF資料
PDF描述
CD4029 CMOS PRESETTABLE UP/DOWN COUNTER
CD4029BH(SMD) CMOS PRESETTABLE UP/DOWN COUNTER
CD4029BE(DIP) CMOS PRESETTABLE UP/DOWN COUNTER
CD4029 Presettable Binary/Decade Up/Down Counter
CD4029BCJ Presettable Binary/Decade Up/Down Counter
相關代理商/技術參數(shù)
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