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參數(shù)資料
| 型號(hào)： | CD40105 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS FIFO Register |
| 中文描述： | FIFO寄存器的CMOS |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | CD40105 |
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All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
CD40105BMS
Chip Dimensions and Pad Layout
FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SHIFT
IN
DATA OUT
READY
8 BIT
DATA
8 BIT
DATA
SHIFT
OUT
DATA IN
READY
*
MASTER
RESET
*
Pulse must be applied for cascading by 16 N bits.
Dimensions in parenthesis are in millimeters and are derived from the basic
inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
BOND PADS:
DIE THICKNESS:
Thickness: 11k
14k
, AL.
10.4k - 15.6k
, Silane
0.004 inches X 0.004 inches MIN
0.0198 inches - 0.0218 inches
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD40105BMS | CMOS FIFO Register(CMOS 先進(jìn)先出寄存器) |
| CD40106BC | Hex Schmitt Trigger(六施密特觸發(fā)器) |
| CD40106BMJ | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85 |
| CD40106 | CMOS HEX SCHMITT TRIGGERS |
| CD40106BMN | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD40105B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CMOS FIFO REGISTER |
| CD40105BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40105BDMSR | 制造商:Intersil Corporation 功能描述:FIFO REGISTER SGL 4-CH CMOS 16CDIP - Rail/Tube |
| CD40105BE | 功能描述:寄存器 CMOS FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| CD40105BEE4 | 功能描述:寄存器 CMOS FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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