參數(shù)資料
型號(hào): CD4006BMS
廠商: Intersil Corporation
英文描述: CMOS 18-Stage Static Register(CMOS 18級(jí) 靜態(tài)寄存器)
中文描述: 的CMOS 18級(jí)靜態(tài)注冊(cè)的CMOS(18級(jí)靜態(tài)寄存器)
文件頁(yè)數(shù): 8/8頁(yè)
文件大小: 77K
代理商: CD4006BMS
665
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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http://www.intersil.com
CD4006BMS
Typical Performance Characteristics
(Continued)
Chip Dimensions and Pad Layout
FIGURE 7. TYPICAL DYANAMIC POWER DISSIPATION
AS A FUNCTION OF CLOCK FREQUENCY
8
6
4
2
8
10
2
6
4
2
2
INPUT FREQUENCY (fCL) (kHz)
1
10
10
3
10
4
8
6
4
2
8
6
4
2
6
4
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
10
4
10
3
10
2
10
P
μ
W
SUPPLY VOLTAGE (VDD) = 15V
10V
5V
10V
CL = 15pF
CL = 50pF
AMBIENT TEMPERATURE (T
A
) = +25
o
C
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10
-3
inch)
Thickness: 11k
14k
, AL.
10.4k - 15.6k
, Silane
METALLIZATION:
PASSIVATION:
BOND PADS:
0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches
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