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參數(shù)資料
| 型號： | CD3206BB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-bit latched/registered/pass-thru Futurebus transceiver |
| 中文描述： | FB SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 187K |
| 代理商： | CD3206BB |
Philips Semiconductors
Product specification
FB2031
9-bit latched/registered/pass-thru Futurebus+ transceiver
1995 May 25
9
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
NOM
UNIT
MIN
4.5
MAX
5.5
V
BIASV
Bias pin voltage
V
CC
= 0 to 5.25V, Bn = 0 to 2.0V
V
CC
= 0 to 4.75V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
V
= 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
B0 – B8 = 0V, Bias V = 5.0V
B0 – B8 = 2V, Bias V = 4.5 to 5.5V
B0 – B8 = 1V, Bias V = 4.5 to 5.5V
V
CC
= 0 to 5.25V, B0 – B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, t
r
= 2ns
V
CC
= 0 to 5.25V, OEB0 = 0.8V
V
CC
= 0 to 2.2V, OEB0 = 0 to 5V
V
CC
= 5.0V
V
I
BIASV
Bias pin DC current
Bias in DC current
1
mA
10
μ
A
V
Bn
I
LM
I
HM
Bus voltage during prebias
Fall current during prebias
Rise current during prebias
Peak bus current during
insertion
1.62
1
-1
2.1
V
μ
A
μ
A
I
Bn
PEAK
10
mA
I
OL
OFF
Power up current
Power u current
100
100
1.0
μ
A
t
GR
Input glitch rejection
1.35
ns
AC ELECTRICAL CHARACTERISTICS
(Industrial)
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C, V
= 5V,
L
= 50pF, R
L
= 500
T
amb
= –40 to +85
°
C,
= 5V
±
10%,
C
L
= 50pF, R
L
= 500
MIN
100
2.3
2.4
2.7
2.5
2.0
2.0
1.2
1.5
1.8
1.7
1.6
1.5
3.0
1.7
UNIT
MIN
120
2.5
2.4
2.9
2.8
2.6
2.4
1.5
1.7
2.1
2.0
1.9
1.7
TYP
150
4.4
4.2
4.6
4.3
4.1
4.7
3.8
3.9
3.5
3.8
3.4
3.2
MAX
MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
TLH
t
THL
Maximum clock frequency
Propagation delay (thru mode)
Bn to An
Propagation delay (transparent latch)
Bn to An
Propagation delay
LCBA to An
Propagation delay
SEL0 or SEL1 to An
Output enable time from High or Low
OEA to An
Output disable time to High or Low
OEA to An
Output transition time, An Port
10% to 90%, 90% to 10%
Output to output skew for multiple
channels
1
Pulse skew
2
t
PHL
– t
PLH
MAX
Waveform 4
MHz
Waveform 1, 2
5.9
5.5
6.2
5.9
5.5
6.1
5.2
6.0
4.8
5.3
4.8
4.8
7.0
6.2
7.1
7.0
6.2
6.8
6.2
6.5
6.0
6.3
5.5
5.5
7.5
4.0
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 5, 6
ns
Waveform 5, 6
ns
Test Circuit and
Waveforms
ns
t
SK
(o)
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Waveform 2
0.5
1.0
1.0
ns
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
tests should be performed last.
4. Due to test equipment limitations, actual test conditions are V
= 1.8V and V
= 1.3V for the B side.
5. For B port input voltage between 3 and 5 volts I
IH
will be greater than 100
μ
A, but the parts will continue to function normally.
6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
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