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參數(shù)資料
| 型號(hào)： | CD3206BB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-bit latched/registered/pass-thru Futurebus transceiver |
| 中文描述： | FB SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 187K |
| 代理商： | CD3206BB |
Philips Semiconductors
Product specification
FB2031
9-bit latched/registered/pass-thru Futurebus+ transceiver
1995 May 25
10
AC ELECTRICAL CHARACTERISTICS
(Industrial)
B PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C, V
= 5V,
C
D
= 30pF, R
U
= 16.5
T
amb
= –40 to +85
°
C,
= 5V
±
10%,
C
D
= 30pF, R
U
= 16.5
MIN
1.5
1.5
1.5
1.5
1.5
1.5
2.0
1.0
1.0
1.0
0.9
0.6
UNIT
MIN
1.0
1.0
1.0
1.0
2.0
1.5
2.0
1.5
1.5
1.2
1.0
0.6
TYP
3.0
2.7
3.2
3.1
4.0
4.0
3.5
2.3
3.0
2.4
MAX
5.0
4.0
5.0
4.2
5.5
5.5
5.5
4.5
5.0
4.5
2.0
3.0
MAX
5.7
4.5
5.5
5.0
6.5
6.0
6.1
5.5
5.7
5.5
3.0
3.0
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
TLH
t
THL
Propagation delay (thru mode)
An to Bn
Propagation delay (transparent latch)
An to Bn
Propagation delay
LCAB to Bn
Propagation delay
SEL0 or SEL1 to Bn
Enable/disable time
OEB0 or OEB1 to Bn
Output transition time, Bn Port
(1.3V to 1.8V)
Output to output skew for multiple
channels
1
Pulse skew
2
t
PHL
– t
PLH
MAX
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Waveform 1, 2
ns
Test Circuit and
Waveforms
ns
t
SK(o)
Waveform 3
1.0
0.4
1.6
1.6
ns
t
SK
(p)
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1.
t
PN
actual – t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
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