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參數(shù)資料
| 型號： | CB35000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS STANDARD CELLS |
| 中文描述： | HCMOS標(biāo)準(zhǔn)單元 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 166K |
| 代理商： | CB35000 |
7/16
CB35000 SERIES
shift register and adders. Macrofunctions are
implemented at layout by utilizing macrocells and
interconnecting to create the logic function.
MODULE GENERATORS
A series of module generators using compiled
cell generation techniques, are available to
support a range of megacells. These modules
enable the designer to choose individual
parameters in order to create a compiled cell,
which
meets
the
requirements. These include single port RAM,
dual port RAM, ROM and MULT. The compiled
cell generators construct custom cells, which are
implemented using a special leaf cell technique,
ensuring predictable layout and accurate module
characteristics.
In choosing megacells the
designer can consider the trade-offs between
speed and area to generate a fully customized
cell
which
meets
their
requirements. These megacell generators are
complemented by a group of application specific
embedded megacells. These allow access to
technologies that have been hitherto the domain
of standard products. Examples include mixed
mode cells for graphics, DAC/ADC’s (4-9 bit),
PLL applications, and Digital Signal Processor
functions for cellular comms, fax and high-speed
modem.which initially consist of a Triple 8-bit
DAC, Graphics RAM, Clock Multiplier PLL and
Frequency Synthesis PLL.
specific
application
specific
device
Table 5
Module Generator Library
Cell
Description
SPRAM
256K bits max
16K word max 64 bit max
Zero static current, Tristate outputs
DPRAM
128K bits max
8K word max 64 bit max
Zero static current, Tristate outputs
ROM
2M bits max
32K word max 64 bit max
Diffusion programmable, Tristate outputs
MULT
Parallel asynchronous operation
2’s complement product
6 to 64 bits for both inputs
Ripple Carry or Fast Carry Look Ahead
100 Mbps serial transputer links coupled with
large and fast memory can be used for pipelining,
caching and synchro circuits in modern RISC
computing architectures. Viterbi and Reed
Solomon cores aim at the HDTV and satellite
transmission markets. To support telecom needs
for CCITT standard applications, ADPCM cells
supporting CT2 protocol have been developed.
DESIGN FOR TESTABILITY
The time and cost for ASIC testing increases
exponentially as the complexity and size of the
ASIC grows. Using a design for testability
methodology allows large, more complex ASICs
to be efficiently and economically tested.
CB35000 supports the JTAG boundary Scan and
both edge and level sensitive scan design
techniques
by
providing
macrocells. Scan testing aids device testability by
permitting access to internal nodes without
requiring a separate external connection for each
node accessed. Testability is assured at device
level with the close coupling of LSSD latch
elements, Automatic Test Pattern Generation
(ATPG)
and
high
architecture. BIST options for memory generators
are also available.
the
necessary
pattern
depth
tester
At system level, SGS-THOMSON fully supports
IEEE 1149.1, and the I/O structure utilized in this
family is completely compatible. Several types of
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