參數(shù)資料
型號: CB35000
廠商: 意法半導體
英文描述: HCMOS STANDARD CELLS
中文描述: HCMOS標準單元
文件頁數(shù): 2/16頁
文件大?。?/td> 166K
代理商: CB35000
CB35000 SERIES
2/16
GENERAL DISCRIPTION
The CB35000 standard cell series uses a high
performance, low voltage, triple level metal,
HCMOS5S 0.5 micron process to achieve sub-
nanosecond internal speeds while offering very
low power dissipation and high noise immunity.
With an average gate density of 5500 gates/mm
2
,
the CB35000 family allows the design of highly
complex devices. The potential available gate
count ranges above 1.5 Million equivalent gates.
Devices can operate over a Vdd voltage range of
2.7 to 3.6 volts.
The I/O count for this array family ranges to over
600 signals and 800 pins dependent upon the
package technology utilized. A Sea of I/O
approach has been followed to give a solution to
CONVENTIONAL VIA LAYOUT
STACKED VIA LAYOUT
SUBSTRATE
ISOLATION
GATE
CONTACT
METAL 1
METAL 2
METAL 3
1st VIA
2nd VIA
3rd DIELECTRIC
2nd DIELECTRIC
1st DIELECTRIC
AREA SAVINGS UP TO 20% FOR RANDOM LOGIC
SIMPLIFIED ROUTING AND DESIGN RULE CHECKING
CONTACT / VIA
PLUGS
Figure 1
Advantages of stacked contacts and vias
today’s problems of drive levels and specialized
interface standards. The technology does not
utilize a set bond pad spacing but allows for pad
spacings from 80 microns upwards. The I/O is
fully compatible with that of the ISB35000
Structured Array family.
The I/O can be configured for circuits ranging
from low voltage CMOS and TTL to 350 mHz
plus low swing differential circuits. Standards like
GTL, SCSI-2, 3.3 Volt PCI, CTI, and a limited set
of 5.0 Volt interfaces are currently being
addressed. A specialized set of impedance
matched transmission line driver LVTTL type
circuits are also available with 25, 35, 45, and 55
Ohm output impedance. These buffers sacrifice
direct current capabilities for matching positive
and negative voltage and current waveforms.
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