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參數(shù)資料
| 型號： | CAT24C161 |
| 英文描述： | Supervisory Circuits with I 2 C Serial CMOS E 2 PROM, Precision Reset Controller and Watchdog Timer(帶16K IIC串行CMOS EEPROM，精密復(fù)位控制器和看門狗定時器的監(jiān)控電路) |
| 中文描述： | 監(jiān)控電路與I 2 C串行的CMOS 2 PROM的位置，精密復(fù)位控制器和看門狗定時器（帶16K的進(jìn)口證的CMOS串行EEPROM的，精密復(fù)位控制器和看門狗定時器的監(jiān)控電路） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CAT24C161 |
CAT24CXX1/XX2
7
Advanced
Doc. No. 25079-00 1/98 M-1
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 5. Acknowledge Timing
Figure 6. Slave Address Bits
FUNCTIONAL DESCRIPTION
The CAT24CXXX supports the I
2
C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24CXXX
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24CXXX monitors the
SDA and SCL lines and will not respond until this
condition is met.
1
0
1
0
X
X
X
R/W
1
0
1
0
X
X
a8
R/W
24C021/022
24C041/042
1
0
1
0
X
a9
a8
R/W
1
0
1
0
a10
a9
a8
R/W
24C081/082
24C161/162
* 'X' Corresponds to Don't Care Bits (can be a zero or a one)
** a8, a9 and a10 correspond to the address of the memory array address word.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particu-
lar slave device it is requesting. The four most significant
bits of the 8-bit slave address are fixed as 1010.
The next three bits (Fig. 6) define memory addressing.
For the 24C021/022, the three bits are don't care. For
the 24C041/042, the next two bits are don't care and the
third bit is the high order address bit. For the 24C081/
082, the next bit is don't care and the successive bits
define the higher order address bits. For the 24C161/
162 the three bits define higher order bits.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24CXXX monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24CXXX then performs a Read or Write operation
depending on the state of the R/
W
bit.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24C163PI-42 | 制造商:ON Semiconductor 功能描述:EEPROM-EEPROM: SERIAL |
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| CAT24C164WGI-26781 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C164WI | 制造商:CSI 功能描述: |
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