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參數(shù)資料
| 型號： | CAT24C161 |
| 英文描述： | Supervisory Circuits with I 2 C Serial CMOS E 2 PROM, Precision Reset Controller and Watchdog Timer(帶16K IIC串行CMOS EEPROM，精密復位控制器和看門狗定時器的監(jiān)控電路) |
| 中文描述： | 監(jiān)控電路與I 2 C串行的CMOS 2 PROM的位置，精密復位控制器和看門狗定時器（帶16K的進口證的CMOS串行EEPROM的，精密復位控制器和看門狗定時器的監(jiān)控電路） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CAT24C161 |
CAT24CXX1/XX2
5
Advanced
Doc. No. 25079-00 1/98 M-1
PIN DESCRIPTIONS
WP
: WRITE PROTECT
If the pin is tied to V
CC
the entire memory array becomes
Write Protected (READ only). When the pin is tied to V
SS
or left floating normal read/write operations are allowed
to the device.
SCL
: SERIAL CLOCK
The serial clock input clocks all data transferred into or
out of the device.
RESET/
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins the
device will initiate and maintain a reset condition for
approximately 200ms. RESET pin must be connected
through a pull-down and
RESET
pin must be connected
through a pull-up device.
RESET
: RESET I/O
SDA:
SERIAL DATA/ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs. In the 24CXX1, the
SDA line is also used as the Watchdog Timer Monitor.
DEVICE OPERATION
Reset Controller Description
The CAT24CXXX provides a precision RESET control-
ler that ensures correct system operation during brown-
out and power-up/down conditions. It is configured
with open drain RESET outputs. During power-up, the
RESET outputs remain active until V
CC
reaches the
V
TH
threshold and will continue driving the outputs for
approximately 200ms (t
PURST
) after reaching V
TH.
After
the t
PURST
timeout interval, the device will cease to drive
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/pull down
devices. During power-down, the RESET outputs will
begin driving active when V
CC
falls below V
TH.
The
RESET outputs will be valid so long as V
CC
is >1.0V
(V
RVALID
).
The RESET pins are I/Os; therefore, the CAT24CXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 24CXXX will initiate a reset timeout
after detecting a high and the
RESET
input in the
24CXXX will initiate a reset timeout after detecting a low.
Watchdog Timer
The Watchdog Timer provides an independent protec-
tion for microcontrollers. During a system failure, the
CAT24CXX1 will respond with a reset signal after a time-
out interval of 1.6 seconds for lack of activity. 24CXX1
is designed with the Watchdog Timer feature on the SDA
input. For the 24CXX1, if the microcontroller does not
toggle the SDA input pin within 1.6 seconds the Watch-
dog Timer times out. This will generate a reset condition
on reset outputs. The Watchdog Timer is cleared by any
transition on SDA.
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared. 24CXX2 does
not feature the Watchdog Timer function.
Figure 1. RESET Output Timing
GLITCH
t
V
CC
PURST
t
PURST
t
RPD
t
RVALID
V
V
TH
RESET
RESET
RPD
t
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| CAT24C164WGI-26781 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
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