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參數(shù)資料
| 型號： | CA91 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS AccelArray |
| 中文描述： | 的CMOS AccelArray |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 97K |
| 代理商： | CA91 |
CA91 Series
6
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DESIGN METHODOLOGY
To make development faster, the number of layers customizable in AccelArray is restricted to 3 to 4. Blocks
that do not need to be redesigned for each product can be designed once and then incorporated into the
architecture. As only 3 to 4 customizable layers are available for development of each product, the requirements
of the layout tool are low. The requirements for timing design, where excessive complexity causes convergence
to be slow, are also low. As result, the time required for design work is reduced. Primarily, tools supplied by
Fujitsu are used for logic design.
A special-purpose tool is used to determine the pin layout. This produces speedy and reliable results.
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SUPPORT TOOL
Frame estimation
FUJITSU LIMITED : FESTA
Pin assignment
FUJITSU LIMITED : PASTEL
Logic synthesis
Synopsys, Inc. : Design Compiler, Cadence Design Systems, Inc. : BuildGates
Physical synthesis
Synplicity, Inc. : Amplify AccelAllay
Format verification
Cadence Design Systems, Inc. : Conformal ASIC, Synopsys, Inc. : Formality
FUJITSU LIMITED : ASSURE
Delay calculation
FUJITSU LIMITED : LCADFE
Timing analysis
Synopsys, Inc. : PrimeTime, FUJITSU LIMITED : GISTA
Simulation
Cadence Design Systems, Inc. : NC-Verilog/NC-VHDL, Synopsys, Inc. : VCS,
Mentor Graphics Corporation : ModelSim, FUJITSU LIMITED : LCADFE
Layout
FUJITSU LIMITED : AccelBuilder
Power calculation
FUJITSU LIMITED : PScope
Power analysis
Cadence Design Systems, Inc. : VoltageStorm
Test synthesis
FUJITSU LIMITED : DFTPlanner
ATPG
FUJITSU LIMITED : FANTCAD/X-Pax/TERBAN
Validation
FUJITSU LIMITED : LCADVL
Fault simulation
FUJITSU LIMITED : FANSCAD
Note : The company names and the product names are the trademarks or registered trademarks of their respective
owners.
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