參數(shù)資料
型號(hào): CA91
廠商: Fujitsu Limited
英文描述: CMOS AccelArray
中文描述: 的CMOS AccelArray
文件頁數(shù): 2/8頁
文件大?。?/td> 97K
代理商: CA91
CA91 Series
2
MACRO LIBRARY
1.
Unit cell
Flip Flop, with clear/preset (support for Mux-D Scan, with Lock up latch)
Clock Buffer
Other combination circuits (approximately 50 different types)
2.
APLL
Input frequency
Output frequency : 400 MHz to 800 MHz
User frequency
: 25 MHz to 800 MHz
Phase shift
: 0/90/180/270 deg.
: 25 MHz to 800 MHz
3.
SRAM
1R1W-SRAM : 32 words
×
40 bits
2RW-SRAM : 512 words
×
40 bits
Bit Select 1 : 1, 2 : 1, 4 : 1, 8 : 1
1 RW operation accesses specified port bit-width
4.
I/O
HSTL *
1
2.5 V LVCMOS
PCML
LVDS
SSTL2
PCI-66 *
2
PCI-X *
2
3.3 V tolerant
(250 MHz)
(200 MHz (input buffer), 75 MHz to 100 MHz (output buffer))
(250 MHz)
(311 MHz)
(250 MHz)
(66 MHz)
(133 MHz)
(200 MHz (input buffer), 75 MHz to 100 MHz (output buffer))
*1 : Needs 1.5 V power supply
*2 : As the I/F is 3.3V tolerant, it does not satisfy the PCI standard in some cases.
Dedicated for Giga Frame
SPI-4P2
XAUI
Fibre Channel
Serial Rapid IO
PCI Express
5.
Memory interface
DDR-SDRAM
QDR-SDRAM
Peer to Peer SDR (200 Mbps)
Peer to Peer DDR (200 Mbps)
SDR-SDRAM
(622 Mbps to 800 Mbps)
(3.125 Gbps)
(1.0 Gbps, 2.0 Gbps)
(1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
(2.5 Gbps)
(400 Mbps)
(400 Mbps)
(167 Mbps)
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