參數(shù)資料
型號(hào)： C9812
廠商： Cypress Semiconductor Corp.
英文描述： Low EMI Clock Generator for Intel 810E Chipset Systems
中文描述： 低EMI時(shí)鐘發(fā)生器芯片組為Intel 810E規(guī)定系統(tǒng)
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 279K
代理商： C9812
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 10 of 18
APPROVED PRODUCT
C9812
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65oC to + 150oC
0oC to +70oC
2KV
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin capacitance
Clock Stablization Time
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Symbol
VIL1
VIH1
VIL2
VIH2
IIL
IIH
Ioz
Idd3.3V
Idd2.5V
Isdd
Cin
Cout
Lpin
tstab
Cxtal
V
BIAS
Txs
Min
Typ
Max
Units
Vdc
Vdc
Vdc
Vdc
μA
μA
μA
mA
mA
μA
pF
pF
nH
mSec
pF
V
μ
S
Conditions
-
-
-
-
-
1.0
-
1.0
-
-5
5
10
280
100
300
5
6
7
-
38
0.7Vdd
40
2.0
-
2.2
-66
Note 1
Note 2
For internal Pull up resistors,
Notes 1,3
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
-
Sel2 = Sel1 = Sel0 = 1, Note 4
Sel2 = Sel1 = Sel0 = 1, Note 4
Sel2 = Sel1 = Sel0 = x, Note 4
Measured from VDD – 3.15 volts
Measured from Pin to Ground. Note 5
32
34
0.3Vdd
-
Vdd/2
-
From Stable 3.3V power supply.
VDD=VDDS = 3.3V
±
5
%, VDDC = VDDI = 2.5
±
5%, TA = 0o to +70oC
Applicable to input signals: Sel(0:1), PD#
Applicable to Sdata, and Sclk.
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. Internal Pull-down resisters
are typically 70K in value.
All outputs loaded as per table below.
Although the device will reliably interface with crystals of a 17pF – 20pF C
L
range, it is optimized to interface with a typical C
L
= 18pF
crystal specifications.
Note1:
Note2:
Note3:
Note4:
Note5:
Clock Name
CPU, IOAPIC, REF, USB
PCI, SDRAM, 3V66(0,1)
DOT
Max Load (in pF)
20
30
15
Table 5.
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