If the internal voltage regulator is not used, the VREGIN in" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� C8051F587-IM
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 347/356闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC 8051 MCU 96K FLASH 32-QFN
鎳�(y墨ng)鐢ㄨ鏄庯細 LIN Bootloader AppNote
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Serial Communication Overview
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 73
绯诲垪锛� C8051F58x
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 50MHz
閫i€氭€э細 SMBus锛�2 绶�/I²C锛�锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 25
绋嬪簭瀛樺劜鍣ㄥ閲忥細 96KB锛�96K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 8.25K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.25 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 25x12b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 32-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� 336-1579-5
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C8051F58x/F59x
90
Rev. 1.2
If the internal voltage regulator is not used, the VREGIN input should be tied to VDD, as shown in
Figure 10.2. External Capacitors for Voltage Regulator
Input/Output鈥擱egulator Disabled
SFR Address = 0xC9; SFR Page = 0x00
SFR Definition 10.1. REG0CN: Regulator Control
Bit
7
6
5
4
3
2
1
0
Name
REGDIS
Reserved
REG0MD
DROPOUT
Type
R/W
R
R/W
R
Reset
0
1
0
1
0
Bit
Name
Function
7
REGDIS
Voltage Regulator Disable Bit.
0: Voltage Regulator Enabled
1: Voltage Regulator Disabled
6
Reserved
Read = 1b; Must Write 1b.
5
Unused
Read = 0b; Write = Don鈥檛 Care.
4
REG0MD
Voltage Regulator Mode Select Bit.
0: Voltage Regulator Output is 2.1V.
1: Voltage Regulator Output is 2.6V.
3:1
Unused
Read = 000b. Write = Don鈥檛 Care.
0
DROPOUT
Voltage Regulator Dropout Indicator.
0: Voltage Regulator is not in dropout
1: Voltage Regulator is in or near dropout.
VREGIN
VDD
4.7 F
.1 F
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鍙冩暩(sh霉)鎻忚堪
C8051F587-IMR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 96 kB 8 kB SPI 2xUART RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
C8051F587-IQ 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50MIPS 96kB 8kB SPI 2xUART I2C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
C8051F587-IQR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 96 kB 8 kB SPI 2xUART RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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C8051F588-IMR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 128 kB 8 kB CAN2.0 LIN 2.1 SPI RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT