SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) The SM" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� C8051F023R
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 94/272闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC 8051 MCU 64K FLASH 64TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� C8051F02x
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 25MHz
閫i€氭€э細 EBI/EMI锛孲MBus锛�2 绶�/I²C锛夛紝SPI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 64KB锛�64K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 4.25K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x8b锛�8x10b; D/A 2x12b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-TQFP
鍖呰锛� 鍓垏甯� (CT)
鍏跺畠鍚嶇ū锛� 336-1035-1
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C8051F020/1/2/3
Rev. 1.4
183
18.
SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0)
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the
system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the
data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is avail-
able to accommodate devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides
control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP
control and generation. SMBus0 is controlled by SFRs as described in Section 18.4 on page 189.
Figure 18.1. SMBus0 Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write to
SMB0DAT
SMBUS CONTROL LOGIC
Read
SMB0DAT
SMB0ADR
S
L
V
6
G
C
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
S
L
V
0
C
R
O
S
B
A
R
Clock Divide
Logic
SYSCLK
SMB0CR
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
SCL
FILTER
N
SDA
Control
0000000b
7 MSBs
8
A
B
A=B
8
0
1
2
3
4
5
6
7
SMB0DAT
8
SMB0CN
S
T
A
S
I
A
F
T
E
T
O
E
N
S
M
B
U
S
Y
S
T
O
SMB0STA
S
T
A
4
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
SCL
Control
Status Generation
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
IRQ Generation
S
T
A
5
S
T
A
6
S
T
A
7
A
B
A=B
SMBUS
IRQ
Interrupt
Request
Port I/O
1
0
SDA
FILTER
N
7
鐩搁棞(gu膩n)PDF璩囨枡
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