C8051F020/1/2/3
Rev. 1.4
201
19.4.
SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Reg-
ister, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special
function registers related to the operation of the SPI0 Bus are described in the following section.
Figure 19.5. SPI0CFG: SPI0 Configuration Register
Bit7:
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
Bit6:
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Bits5-3:
BC2-BC0: SPI0 Bit Count.
Indicates which of the up to 8 bits of the SPI0 word have been transmitted.
Bits2-0:
SPIFRS2-SPIFRS0: SPI0 Frame Size.
These three bits determine the number of bits to shift in/out of the SPI0 shift register during a data
transfer in master mode. They are ignored in slave mode.
R/W
R
R/W
Reset Value
CKPHA
CKPOL
BC2
BC1
BC0
SPIFRS2
SPIFRS1
SPIFRS0
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x9A
BC2-BC0
BIT Transmitted
000
Bit 0 (LSB)
001
Bit 1
010
Bit 2
011
Bit 3
100
Bit 4
101
Bit 5
110
Bit 6
111
Bit 7 (MSB)
SPIFRS
Bits Shifted
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
