C8051F020/1/2/3
Rev. 1.4
241
Figure 22.20. TMR3CN: Timer 3 Control Register
Bit7:
TF3: Timer3 Overflow Flag.
Set by hardware when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 3 Interrupt service routine. This bit is
not automatically cleared by hardware and must be cleared by software.
Bits6-3:
UNUSED. Read = 0000b, Write = don't care.
Bit2:
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3.
0: Timer 3 disabled.
1: Timer 3 enabled.
Bit1:
T3M: Timer 3 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 3.
0: Counter/Timer 3 uses the system clock divided by 12.
1: Counter/Timer 3 uses the system clock.
Bit0:
T3XCLK: Timer 3 External Clock Select
This bit selects the external oscillator input divided by 8 as the Timer 3 clock source. When T3XCLK
is logic 1, bit T3M (TMR3CN.1) is ignored.
0: Timer 3 clock source defined by bit T3M (TMR3CN.1).
1: Timer 3 clock source is the external oscillator input divided by 8.
R/W
Reset Value
TF3
-
TR3
T3M
T3XCLK
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x91
Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte
Bits 7-0:
TMR3RLL: Timer 3 Reload Register Low Byte.
Timer 3 is configured as an auto-reload timer. This register holds the low byte of the reload value.
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x92