參數(shù)資料
型號: C8051F015
廠商: Cygnal Technologies
英文描述: 25 MIPS,32k Flash,2.25k Ram,10bit ADC,64 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,10位 ADC,64 腳 MCU)
中文描述: 25 MIPS的,32K閃存,2.25k羊,10位ADC,64引腳微控制器(25 MIPS的,32K的閃速存儲器,2.25k羊,10位ADC和64腳微控制器)
文件頁數(shù): 41/170頁
文件大小: 1294K
代理商: C8051F015
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc.
2001
Page 41
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
6.2.
The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before
performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC
conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or
16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate different
system clock speeds.
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
4. A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC0CN. Converted data is available
in the ADC data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be either left or right justified
in the ADC0H:ADC0L register pair (see example in Figure 6.9) depending on the programmed state of the ADLJST
bit in the ADC0CN register.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different low
power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;
3. Tracking is active only when the CNVSTR input is low;
4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the
ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In
this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also
be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
ADC Modes of Operation
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CNVSTR
(ADSTM[1:0]=10)
ADCTM=1
Track
Convert
Low Power Mode
ADCTM=0
Track Or Convert
Convert
Track
Low Power or
Convert
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
ADCTM=1
Track
Convert
Low Power Mode
ADCTM=0
Track or Convert
Convert
Track
Low Power or
Convert
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
SAR Clocks
SAR Clocks
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SAR Clocks
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C8051F015-GQR 功能描述:8位微控制器 -MCU 32KB 10ADC 64Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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