參數(shù)資料
型號(hào): C8051F015
廠商: Cygnal Technologies
英文描述: 25 MIPS,32k Flash,2.25k Ram,10bit ADC,64 Pin MCU(25 MIPS,32k 閃速存儲(chǔ)器,2.25k Ram,10位 ADC,64 腳 MCU)
中文描述: 25 MIPS的,32K閃存,2.25k羊,10位ADC,64引腳微控制器(25 MIPS的,32K的閃速存儲(chǔ)器,2.25k羊,10位ADC和64腳微控制器)
文件頁數(shù): 112/170頁
文件大?。?/td> 1294K
代理商: C8051F015
Page 112
CYGNAL Integrated Products, Inc.
2001
4.2001; Rev. 1.3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
16. SMBus
The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1.1. It is a
two-wire, bi-directional serial bus, which is also compatible with the I
2
C serial bus. Reads and writes to the interface
by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of
the data. Data can be transferred at up to 1/8
th
of the system clock if desired (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is used to
accommodate devices with different speed capabilities on the same bus.
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver, and
data transfers from an addressed slave transmitter to a master receiver. The master device initiates both types of data
transfers and provides the serial clock pulses. The SMBus interface may operate as a master or a slave. Multiple
master devices on the same bus are also supported. If two or more masters attempt to initiate a data transfer
simultaneously, an arbitration scheme is employed with a single master always winning the arbitration.
Figure 16.1. SMBus Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write to
SMB0DAT
SMBUS CONTROL LOGIC
Read
SMB0DAT
SMB0ADR
S
L
V
6
G
C
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
S
L
V
0
C
R
O
S
S
B
A
R
Clock Divide
Logic
SYSCLK
SMB0CR
C
R
5
4
C
R
7
C
R
6
C
R
C
R
3
C
R
2
C
R
1
C
R
0
SCL
FILTER
N
SDA
Control
0000000b
7 MSBs
8
A
B
A
8
0
1
2
3
4
5
6
7
SMB0DAT
8
SMB0CN
S
T
A
O
S
I
A
A
F
T
E
T
O
E
E
N
S
M
B
B
U
S
Y
S
T
SMB0STA
S
T
A
4
5
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
SCL
Control
Status Generation
SCL Generation (Master Mode)
IRQ Generation
Arbitration
SCL Synchronization
S
T
A
S
T
A
6
S
T
A
7
A
B
A
SMBUS
IRQ
Interrupt
Request
Port I/O
1
0
SDA
FILTER
N
7
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C8051F015-GQR 功能描述:8位微控制器 -MCU 32KB 10ADC 64Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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