參數(shù)資料
型號: C3ENPB0-DS
英文描述: 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
中文描述: ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂買0
文件頁數(shù): 74/114頁
文件大?。?/td> 1893K
代理商: C3ENPB0-DS
74
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
Power Sequencing
It is intended that the VDD33/VDDT and VDD rails are sequenced to their final value
together for most applications. VDD33 and VDDT must be above VDD at all times. VDD
must be brought to its final value within 100ms of sequencing on VDD33 and VDDT.
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-3e NP
Figure 9
indicates the relationship between the clocks and PRSTX. There is no requirement that the
asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be
asserted within 100
μ
s of power initiation. Typically, reset is held low during power
initiation.
Figure 9
Bringup Clock Timing Diagram
TCLKI, PCLK,
SCLK, SCLKX,
MDCLK, FTXCLK,
FRXCLK
PRSTX
3
1ms
3
100
μ
s
(
(
)
)
100
μ
s
VDD, VDD33,
VDDT
F
n
.
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