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| 型號(hào)： | C3ENPB0-DS |
| 英文描述： | 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM |
| 中文描述： | ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂買0 |
| 文件頁(yè)數(shù)： | 52/114頁(yè) |
| 文件大小： | 1893K |
| 代理商： | C3ENPB0-DS |
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52
CHAPTER 2: SIGNAL DESCRIPTIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
MRASX
A23
1
LVTTL
O
PD
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
MWEX
A22
1
LVTTL
O
PD
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
MCSX
A25
1
LVTTL
O
PD
Chip Select: MCSX enables (registered LOW) and
disables (registered HIGH) the command decoder.
All commands are masked when MCSX is
registered HIGH. MCSX provides the external bank
selection on systems with multiple banks. MCSX is
considered part of the command code.
MDQM
MDQML
A20
A21
1
1
LVTTL
LVTTL
O
PD
O
PD
Input/Output Mask: MDQM is an input mask
signal for write accesses and an output enable
signal for read accesses. Input data is masked
when MDQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a high Z
state (two-clock latency) when MDQM is sampled
HIGH during the READ cycle.
NOTE: MDQML is an identical copy of MDQM
used to drive the loading on SDRAM
configurations with 2 DQM pins.
MDCLK
A26
1
LVTTL
I
PD
Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of the MDCLK. MDCLK also increments the
internal burst counter and controls the output
registers.
TOTAL PINS
160
Table 22
BMU SDRAM Interface Signals (continued)
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
F
n
.
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| C3F002KBS | 制造商:Hammond Power Solutions 功能描述:TRANSFORMER, DISTRIBUTION , ENCAPSULATED, 480V IN, 208Y/120V OUT, 2KVA |
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