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| 型號(hào)： | BXM80532GC1800D |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 67/81頁 |
| 文件大?。?/td> | 598K |
| 代理商： | BXM80532GC1800D |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
67
Table 35. BSEL[1:0] Encoding
BSEL[1:0]
System Bus Frequency
00
66 MHz
01
100 MHz
10
Reserved
11
Reserved
CLKREF (Analog)
The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip
point for the BCLK signal. This signal should be connected to a resistor divider to generate 1.25V
from the 2.5V supply.
CMOSREF (Analog)
The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the
CMOS input buffers. A voltage divider should be used to divide a stable voltage plane (e.g., 2.5V
or 3.3V). This signal must be provided with a DC voltage that meets the V
CMOSREF
specification
from Table 12.
D[63:0]# (I/O - GTL+)
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between
both system bus agents, and must be connected to the appropriate pins/balls on both agents. The
data driver asserts DRDY# to indicate a valid data transfer.
DBSY# (I/O - GTL+)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is
deasserted. This signal must be connected to the appropriate pins/balls on both agents on the
system bus.
DEFER# (I - GTL+)
The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the
addressed memory agent or I/O agent. This signal must be connected to the appropriate pins/balls
on both agents on the system bus.
DEP[7:0]# (I/O - GTL+)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data
bus. They are driven by the agent responsible for driving D[63:0]#, and must be connected to the
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