參數(shù)資料
型號(hào)： BU-65527M4-200
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 2094K
代理商： BU-65527M4-200
14
Data Device Corporation
www.ddc-web.com
BU-65528 and BU-65527
F1 web-10/02-0
first and second retry attempts. Retries may be enabled or dis-
abled on an individual message basis.
BC INTERRUPTS
BC interrupts may be enabled by the Interrupt Mask Register for
Stack Rollover, Retry, End-of-Message (global), End-of-
Message (in conjunction with the BC Control Word for individual
messages), response timeout, message error, end of BC frame,
and Status Set conditions. The definition of “Status Set” is pro-
grammable on an individual message basis by means of the BC
Control Word. This allows for masking (“care/don't care”) for the
individual RT Status Word bits.
REMOTE TERMINAL (RT) ARCHITECTURE
The RT protocol design of the BU-65528/27 represents DDC's
fifth generation implementation of a 1553 RT. One of the salient
features of the ACE's RT architecture is its true multiprotocol
functionality. This includes programmable options for support of
MIL-STD-1553A, the various McAir protocols, and MIL-STD-
1553B Notice 2. The BU-65528/27 RT response time is 2 to 5
s
dead time (4 to 7
s per 1553B), providing compliance to all the
Stack B
2F00-2FFF
Not Used
2EE6-2EFF
Message Block 308
2EC6-2EE5
Initial Message Count A (see note)
(Auto-Frame Repeat Mode)
Message Block 2
0154-0179
Message Block 1
012E-0153
Message Block 0
0108-012D
Initial Message Count B (see note)
(Auto-Frame Repeat Mode)
0107
Initial Stack Pointer B (see note)
(Auto-Frame Repeat Mode)
0106
Message Count B
0105
Stack Pointer B
0104
Initial Stack Pointer A (see note)
(Auto-Frame Repeat Mode)
0102
Message Count A (fixed location)
0101
Stack Pointer A (fixed location)
0100
Stack A
0000-00FF
DESCRIPTION
ADDRESS
(HEX)
0103
TABLE 33. TYPICAL BC MEMORY ORGANIZATION
(SHOWN FOR 12K RAM)
Notes:
1) Used only in the Enhanced BC mode with Frame Auto-Repeat
enabled.
2) Address represents the word offset from the memory base
address in the A24 or A32 memory address space.
1553 protocols. Additional multiprotocol features of the BU-
65528/27 include options for full software control of RT Status
and Built-in-Test (BIT) words. Alternatively, for 1553B applica-
tions, these words may be formulated in real-time by the BU-
65528/27 protocol logic.
The BU-65528/27 RT protocol design implements all the MIL-
STD-1553B message formats and dual-redundant mode codes.
This design is based largely on previous generation products
that have passed SEAFAC testing for MIL-STD-1553B compli-
ance. The ACE RT performs comprehensive error checking,
word and format validation, and checks for various RT-to-RT
transfer errors. Other key features of the BU-65528/27 RT
include a set of interrupt conditions, internal command illegaliza-
tion, and programmable busy by subaddress.
RT MEMORY ORGANIZATION
TABLE 34 illustrates a typical memory map for the BU-65528/27
in RT mode. As in BC mode, the two Stack Pointers reside in
fixed locations in the shared RAM address space: address
0100(hex) for the Area A Stack Pointer and address 0104(hex)
for the Area B Stack Pointer. Besides the Stack Pointer, for RT
mode there are several other areas of the ACE address space
designated as fixed locations. All RT modes of operation require
the Area A and Area B Lookup Tables. Also allocated are sever-
al fixed locations for optional features: Command Illegalization
Lookup Table, Mode Code Selective Interrupt Table, Mode Code
Data Table, and Busy Bit Lookup Table. It should be noted that
any unenabled optional fixed location may be used for general
purpose storage (data blocks).
The RT Lookup tables, which provide a mechanism for mapping
data blocks for individual Tx/Rx/Bcst-subaddresses to areas in
the RAM, occupy address range locations 0140 to 01BF for Area
A and 01C0 to 023F for Area B. The RT lookup tables include
Subaddress Control Words and the individual Data Block
Pointers. If used, address range 0300-03FF will be dedicated as
the illegalizing section of RAM. The actual Stack RAM area and
the individual data blocks may be located in any of the nonfixed
areas in the shared RAM address space.
RT MEMORY MANAGEMENT
One of the salient features of the ACE series products is the flex-
ibility of its RT memory management architecture. The RT archi-
tecture allows the memory management scheme for each trans-
mit, receive, or broadcast subaddress to be programmable on a
subaddress basis. Also, in compliance with MIL-STD-1553B
Notice 2, the BU-65528/27 provides an option to separate data
received from broadcast messages from nonbroadcast received
data.
Besides supporting a global-double-buffering scheme (as in BC
mode), the ACE RT provides a pair of 128-word Lookup Tables
for memory management control, programmable on a subad-
dress basis (refer to TABLE 35). The 128-word tables include 32-
word tables for transmit message pointers and receive message
pointers. There is also a third, optional Lookup Table for broad-
cast message pointers, providing Notice 2 compliance, if neces-
sary.
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