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參數(shù)資料
| 型號： | BU-65527M4-200 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA |
| 文件頁數(shù)： | 23/32頁 |
| 文件大?。?/td> | 2094K |
| 代理商： | BU-65527M4-200 |
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Data Device Corporation
www.ddc-web.com
BU-65528 and BU-65527
F1 web-10/02-0
The software interface of each 1553 channel is completely inde-
pendent of the other channels. The operating modes of each of
the BU-65528/27's 1553 channels are controlled through the use
of 30 on-board registers. 1553 message traffic is stored and
retrieved using 12K of shared, memory mapped, on-board RAM.
The 1553 internal registers control and operate the BU-
65528/27. They include the Configuration Registers, Start/Reset
Register, 1553 Time Tag Register, Interrupt Select Register, and
RT Address Register. The Configuration Registers define the
operating mode and various options. The Start/Reset Register
provides reset and BC/MT start signals. The Interrupt Mask
Register enables desired interrupts, with the interrupt priority
level being software programmable by the user.
The RT Address Register is programmed in Configuration
Register #5. The 1553 Time Tag Register is used to time tag
messages in BC, RT and MT modes. The VME/VXI functions are
controlled by the other six registers which include the
Identification Register, Device Type, Status/Control, Offset,
Vector/Enable/Level, and Device Type Extension registers.
The BU-65528/27's 12K x 16 of static RAM is shared by the CPU
and the 1553 Bus with memory arbitration handled automatical-
ly by the BU-65528/27.
The BU-65528/27 will withhold the
signal to the VME/VXI
backplane while a word is being transferred to or from the 1553
Bus. Since the memory arbitration is handled by simply stretch-
ing the handshake cycle, the wait state is transparent to the
CPU's software. A maximum wait of 2.5
s can occur.
In addition to storing the 1553 message data, the RAM imple-
ments the Stacks and Lookup Tables required for the different
modes of operation. A Descriptor Stack is used in both BC, RT
and MT modes. This stack records the status of each message,
the time the message was transmitted or received, and contains
either the received 1553 command (in RT and MT mode), or the
actual address of the 1553 message block (in BC mode). In RT
mode, a Lookup Table is provided to define the addresses of the
data blocks to be used when receiving or transmitting messages
for the individual subaddresses. In MT mode a separate data
stack is used to store the remainder of the message.
BU-65527M AND BU-65527C
The BU-65527M is a Militarized version of the BU-65528 which
is conduction-cooled as per IEEE 1101.2 and is designed to
meet the stringent environmental specifications required by most
military applications.
The BU-65527M routes the 1553 bus connections through the
VME P2 connector. There are no panel-mounted connectors on
the front of the BU-65527X as there are on the BU-65528.
In an effort to eliminate the need for user selectable jumper
blocks (which do not lend themselves to rugged applications) the
register base address of the BU-65527M is selected through
dedicated pins on the VME P2 connector. The 1553 bus connec-
tions on the P2 connector are factory selected for transformer
coupled configuration (contact factory for non-standard direct
coupled configuration). The addressing mode of the BU-
65527M's RAM is factory configured for VME Standard (A24)
DTACK
addressing. Contact factory for version configured for VME
Extended (A32) addressing.
The RT address of each 1553 channel on the BU-65527M is
selected through dedicated pins on the VME P2 connector. A
hardwired RT address ensures the integrity of the address and
precludes the possibility of errant software programming the
wrong RT address which could effect the operation of other ter-
minals on the 1553 bus.
Both the BU-65527X and BU-65528 are implemented with ACE
components. As such the BU-65527X is fully software compati-
ble with the BU-65528 with the only exception being the pro-
gramming of the RT address (BU-65528 RT address is latchable
while the BU-65527X RT address is hardwired through the P2
connector). The BU-65527X utilizes DDC's BU-61585 ACE com-
ponent while the BU-65528 utilizes DDC's BU-61586 ACE com-
ponent.
MEMORY MANAGEMENT
The BU-65528/27 incorporates complete memory management
and processor interface logic. The software interface to the host
processor is implemented by means of on-board registers plus
12K words of RAM. For all three modes, a stack area of RAM is
maintained. In BC mode, the stack allows for the scheduling of
multi-message frames. For all three modes, the stack provides a
real-time chronology of all messages processed. In addition to
the stack processing, the memory management logic performs
storage, retrieval, and manipulation functions involving pointer
and message data structures for all three modes.
The BU-65528/27 provides a number of programmable options
for RT mode memory management. In compliance with MIL-
STD-1553, received data from broadcast messages may be
optionally separated from non-broadcast received data. For each
transmit, receive or broadcast subaddress, either a single-mes-
sage data block or a variable-sized (128 to 8192 words) circular
buffer may be allocated for data storage. In addition to helping
ensure data consistency, the circular buffer feature provides a
means of greatly reducing host processor overhead for bulk data
transfer applications. End-of-message interrupts may be enabled
either globally, following error messages, on a Tx/Rx/Bcst-sub-
address basis, or when any particular Tx/Rx/Bcst-subaddress
circular buffer reaches its lower boundary.
INTERRUPT PROCESSING
Interrupts are enabled by programming the interrupt priority
level, interrupt vector, and interrupt conditions. The interrupt con-
ditions are selected in the interrupt mask register. The BU-
65528/27 generates an interrupt request on the VME/VXI back-
plane and waits for the bus master to initiate an interrupt
acknowledge cycle. Upon receiving an interrupt acknowledge,
the board will place the interrupt vector on bits 7 through 0 of the
data bus and clear the interrupt request. Further interrupts are
disabled until the interrupt is cleared either by an interrupt reset
(in the start reset register) or by reading the interrupt status reg-
ister (if interrupt auto-clear feature is enabled).
Individual interrupts are enabled by the Interrupt Mask Register.
The host processor may easily determine the cause of the inter-
rupt by using the Interrupt Status Register. The Interrupt Status
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