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參數(shù)資料
| 型號： | BU-61705F4-202 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 45/52頁 |
| 文件大?。?/td> | 359K |
| 代理商： | BU-61705F4-202 |
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DMA WRITE OPERATION
In response to a receive command, the BU-61703/5 will need to
transfer data to the subsystem. There are two options for doing
this, the burst mode and the non-burst mode. In burst mode, all
received data words are transferred from the SSRT to the sub-
system in a contiguous burst, only following the reception of the
correct number of valid data words. In the non-burst mode,
single data words are written to the external subsystem imme-
diately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT asserts
low. The
subsystem must then respond with
low. Assuming that
was asserted in time, the BU-61703/5 will then assert
low. The BU-61703/5 will then assert the appropriate
value of L_BRO,
, SA4-0, and MC/CWC4-0,
high,
and
low.
will be asserted low for one clock
cycle. The subsystem may then use either the falling or rising
edge of
to latch the data. Similar to the DMA read oper-
ation, the address outputs CWC4 through CWC0 are increment-
ed after the completion of a DMA write operation.
HANDSHAKE FAIL
Following the assertion of
low by the SSRT, the external
subsystem has 10 s to respond by asserting
to logic
"0".
If the BU-61703/5 (SSRT) asserts
and the subsystem
does not respond with
in time for the BU-61703/5 to
complete a data word transfer, the
output will be assert-
ed low to inform the subsystem of the handshake failure, and bit
12 in the internal Built-In-Test (BIT) word will be set to logic "1."
If the handshake failure occurs on a data word read transfer (for
a transmit command), the SSRT will abort the current message
transmission. In the case of a handshake failure on a write trans-
fer (received command) the SSRT will set the handshake failure
output and BIT word bit, and abort processing the current mes-
sage.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
BU-61703/5 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
The BU-61703/5 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
HSFAIL
DTGRT
DTREQ
DTACK
DTREQ
MEMWR
MEMOE
R
/
T
DTACK
DTGRT
DTREQ
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The BU-61703/5 will not respond to
any MIL-STD-1553 commands or transfer received data from
any non-broadcast messages if an odd parity sum is not pre-
sented by RT_AD_4-0 and RT_AD_P. An address parity error will
be indicated by a low output on the
pin. The input
signal RT_AD_LAT operates a transparent latch for RTAD4-
RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch
tracks the value presented on the input pins. If RT_AD_LAT is
high, the output of the internal latch becomes latched to the val-
ues presented at the time of a low-to-high transition of
RT_AD_LAT.
RT address and RT Address Parity must be presented valid
before the mid-parity crossing of the 1553 command and held, at
least, until following the first received data word.
COMMAND ILLEGALIZATION
The BU-61703/5 includes a provision for command illegalization.
If a command is illegalized, the BU-61703/5 will set the Message
error bit and transmit its status word to the Bus Controller. No
data words will be transmitted in response to an illegalized trans-
mit command. However, data words associated with an illegal-
ized receive command will be written to the external subsystem
(although these transfers may be blocked using external logic).
is sampled approximately 2 s following the mid-parity
bit zero crossing of the received command word. A low on
will illegalize a particular command word and cause the
SSRT to respond with its Message error bit set in its status word.
Command illegalization based on broadcast,
bit, subad-
dress, and/or word count/mode code may be implemented by
means of an external PROM, PLD, or RAM device, as shown in
Figure 2.
The external device may be used to define the legality of specif-
ic commands. Any subset of the possible 1553 commands may
be illegalized as a function of broadcast,
bit, subaddress,
word count, and/or mode code. The output of the illegalization
device should be tied directly to the BU-61703/5's
sig-
nal input. The maximum access time of the external illegalizing
device is 400 ns.
If illegalization is not used,
should be hardwired to logic
"1".
ILLEGAL
R
/
T
R
/
T
ILLEGAL
RT_AD_ERR
5
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| BU-61740B3-102K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
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| BU-61743F4-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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