參數(shù)資料
型號： BU-61705F4-202
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72
文件頁數(shù)： 34/52頁
文件大?。?/td> 359K
代理商： BU-61705F4-202
4
galized as a function of broadcast,
bit, subaddress, word
count, and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The BU-61703/5 provides a number of real-time output signals.
These various signals provide indications of message in
progress, valid received message, message error, handshake
fail, loop-test fail or transmitter timeout.
The BU-61703/5 includes standard DMA handshake signals
(Request, Grant, and Acknowledge) as well as transfer control
outputs (
and
). The DMA interface operates in
a 16-bit mode, supporting word-wide transfers.
The SSRT's system interface allows the BU-61703/5 to be inter-
faced directly to a simple system that doesn't include a micro-
processor. This provides a low-cost 1553 interface for A/D and
D/A converters, switch closures, actuators, and other discrete
I/O signals.
The BU-61703/5 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the BU-61703/5
to transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a
rate of one data word every three clock cycles. Burst mode nego-
tiates only once for use of the subsystem bus. Negotiation is per-
formed only after all 1553 data words have been received and
validated. In non-burst mode, the BU-61703/5 will negotiate for
the local bus after every received data word. The data word
transfer period is three clock cycles for each received 1553 data
word.
The BU-61703/5 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a small amount
of "glue" logic, the BU-61703/5 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a
shared RAM for each broadcast / T/R bit / subaddress / mode
code.
ADDRESS MAPPING:
A typical addressing scheme for the BU-61703/5 12-bit address
bus could be as follows:
A11:
A10:
A9-A5:
SUBADDRESS 4-0
A4-A0:
WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" allo-
cation scheme for the storage of data words. The 12 address out-
RECEIVE
/
TRANSMIT
OWNADDRESS
/
BROADCAST
MEMWR
MEMOE
R
/
T
puts may be used to map into 4K words of processor address
space. The BU-61703/5's addressing scheme maps messages
in terms of broadcast/own address, transmit/receive, subad-
dress, and word/count mode code. A 32-word message block is
allocated for each T/R-subaddress.
For non-mode code messages, the Data Words to be transmit-
ted or received are accessed from (to) relative locations 0
through 31 within the respective message block. For the MIL-
STD-1553B Synchronize with data, Selected transmitter shut-
down, Override selected transmitter shutdown, and Transmit vec-
tor word mode commands which involve a single data word
transfer, the address for the data word is offset from location 0 of
the message block for subaddresses 0 and 31 by the value of the
mode code field of the received command word.
The data words transmitted in response to the Transmit last
command or Transmit BIT word mode commands are accessed
from a pair of internal registers.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals
are provided to facilitate communication with the parallel sub-
system. The data bus D15-D0 consists of bi-directional tri-state
signals. The address bus L_BRO,
, SA4-SA0, and
WC/MC/CWC4-0; along with the data transfer control signals
and
are two-state output signals.
The control signals include the standard DMA handshake sig-
nals
,
, as well as the transfer control
outputs
and
.
provides an indication
to the subsystem of a handshake failure condition.
Data transfers between the subsystem and the BU-61703/5 are
performed by means of a DMA handshake, initiated by the BU-
61703/5. A data read operation is defined to be the transfer of
data from the subsystem to the BU-61703/5. Conversely, a data
write operation transfers data from the BU-61703/5 to the sub-
system. Data is transferred as a single 16-bit word
DMA READ OPERATION
In response to a transmit command, the BU-61703/5 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT asserts the signal
low.
Assuming that the subsystem asserts
in time, the SSRT
will then assert the appropriate values of L_BRO (logic "0"),
(high), SA4-0, and MC/CWC4-0;
high, along with
low and
low to enable data to be read from the
subsystem.
After the transfer of each Data Word has been completed, the
value of the address bus outputs CWC4 through CWC0 is incre-
mented.
MEMOE
DTACK
MEMWR
R
/
T
DTGRT
DTREQ
FAIL
_
HS
MEMWR
MEMOE
DTACK
DTGRT
DTREQ
MEMWR
MEMOE
R
/
T
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