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參數資料
| 型號： | BR93LC56FV |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 2,048-Bit Serial Electrically Erasable PROM |
| 中文描述： | 2,048位串行電可擦除可編程ROM |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 127K |
| 代理商： | BR93LC56FV |
7
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
CS
SK
DI
DO
1
1
2
D15
D14
D0
D1
D14
D15
0
High-Z
1
1
0
0
A6
A5
A1
A0
2
4
11
12
27
28
1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in
succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations.
With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
Fig. 2 Read cycle timing (READ)
(4) Reading (Figure 2)
When the read command is acknowledged, the data
(16 bits) for the input address is output serially. The
data is synchronized with the SK rise during A0 acqui-
sition and a “0” (dummy bit) is output. All further data is
output in synchronization with the SK pulse rises.
(5) Write enable (Figure 3)
These ICs are set to the write disabled state by the in-
ternal reset circuit when the power is turned on.
Therefore, before performing a write command, the
write enable command must be executed. When this
command is executed, it remains valid until a write
disable command is issued or the power supply is cut
off. However, read commands can be used in either
the write enable or write disable state.
(6) Write (Figure 4)
This command writes the input 16-bit data (D15 to D0)
to the specified address (A6 to A0). Actual writing of
the data begins after CS falls (following the 27th clock
pulse after the start bit input), and the SK clock which
reads D0 falls.
If STATUS is not detected (CS is fixed at LOW), or if
STATUS is detected (CS = HIGH) at a maximum of 10
ms, in accordance with the time t
E / W
, no commands
are accepted while DO is LOW (BUSY). Therefore, no
commands should be input during this period.
1
0
0
1
1
CS
SK
DI
DO
High-Z
Fig. 3 Write enable cycle timing
相關PDF資料 |
PDF描述 |
|---|---|
| BR93LC56RF | 2,048-Bit Serial Electrically Erasable PROM |
| BRM-1020-NS | INFRARED RECEIVER MODULE |
| BRM-1020 | INFRARED RECEIVER MODULE |
| BRT11 | Optocoupler, Phototriac Output |
| BRT11-H | Optocoupler, Phototriac Output |
相關代理商/技術參數 |
參數描述 |
|---|---|
| BR93LC56FV-W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| BR93LC56F-W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| BR93LC56F-WE2 | 制造商:ROHM Semiconductor 功能描述:EEPROM Serial 2K-bit 128 x 16 2.5V/3.3V/5V 8-Pin SOP T/R |
| BR93LC56RF | 制造商:ROHM 制造商全稱:Rohm 功能描述:2,048-Bit Serial Electrically Erasable PROM |
| BR93LC56RFJ-W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
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