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參數(shù)資料
| 型號(hào)： | BR93LC56FV |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 2,048-Bit Serial Electrically Erasable PROM |
| 中文描述： | 2,048位串行電可擦除可編程ROM |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | BR93LC56FV |
11
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(6) Connecting DI and DO directly
The BR93LC56 / F / FV have an independent input pin
(DI) and output pin (DO). These are treated as individ-
ual signals on the timing chart but can be controlled
through one control line.Control can be initiated on a
single control line by inserting a resistor R betweeen
the [DI] pin and [DO] pin.
1) Data collision between the
μ
-COM output and the
DO output
Within the input and output timing of the BR93LC56 / F
/ FV, the drive from the
μ
-COM output to the DI input
and a signal output from the DO output can be emitted
at the same time. This happens only for the 1 clock
cycle (a dummy bit “0” is output to the DO pin) which
acquires the A0 address data during a read cycle.
When the address data A0 = 1, the
μ
-COM output
becomes a direct current source for the DO pin.
The resistor R is the only resistance which limits this
current. Therefore, a resistor with a value which satis-
fies the
μ
-COM and the BR93LC56 / F / FV current
capacity is required. When using a single control line,
when a dummy bit “0” is output to the DO, the
μ
-COM
I / O address data A0 is also output. Therefore, the
dummy bit cannot be detected.
2) Feedback to the DI input from the DO output
Data is output from the DO pin and then feeds back
into the DI input through the resistor R. This happens
when:
· DO data is output during a read operation
· A READY / BUSY signal is output during WRITE or
WRAL operation
Such feedback does not cause problems in the basic
operation of the BR93LC56 / F / FV.
The
μ
-COM input level must be adequately maintained
for the voltage drop at R which is caused by the total
input leakage current for the
μ
-COM and the BR93-
LC56 / F / FV.
In the state in which SK is input, when the READY /
BUSY function is used, make sure that CS is dropped
to LOW within four clock pulses of the output of the
READY signal HIGH and the standby mode is restored.
For input after the fifth clock pulse, the READY HIGH
will be taken as the start bit and WDS or some other
mode will be activated, depending on the DI state.
μ
-COM
I / O PORT
R
DI
DO
BR93LC56
Fig. 11 Common connections for
the DI and DO control line
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BR93LC56RF | 2,048-Bit Serial Electrically Erasable PROM |
| BRM-1020-NS | INFRARED RECEIVER MODULE |
| BRM-1020 | INFRARED RECEIVER MODULE |
| BRT11 | Optocoupler, Phototriac Output |
| BRT11-H | Optocoupler, Phototriac Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BR93LC56FV-W | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microwire Serial EEPROM |
| BR93LC56F-W | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microwire Serial EEPROM |
| BR93LC56F-WE2 | 制造商:ROHM Semiconductor 功能描述:EEPROM Serial 2K-bit 128 x 16 2.5V/3.3V/5V 8-Pin SOP T/R |
| BR93LC56RF | 制造商:ROHM 制造商全稱(chēng):Rohm 功能描述:2,048-Bit Serial Electrically Erasable PROM |
| BR93LC56RFJ-W | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microwire Serial EEPROM |
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