參數(shù)資料
型號(hào): BR93LC56FV
廠商: Rohm CO.,LTD.
英文描述: 2,048-Bit Serial Electrically Erasable PROM
中文描述: 2,048位串行電可擦除可編程ROM
文件頁(yè)數(shù): 6/12頁(yè)
文件大小: 127K
代理商: BR93LC56FV
6
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(3) Timing chart
CS
SK
DI
DO (READ)
DO (WRITE)
STATUS VALID
t
DF
t
DF
t
PD1
t
PD0
t
DIH
t
DIS
t
CSS
t
CSH
t
SKH
t
SKL
Data is acquired from DI in synchronization with the SK rise.
During a reading operation, data is output from DO in synchronization with the SK rise.
During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time t
CS
after CS falls following the input of a write
command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.
After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
Fig. 1 Synchronized data timing
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