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參數(shù)資料
| 型號： | BR34L02FV-W |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 256? bit Electrically Erasable PROM |
| 中文描述： | 256？位電可擦除可編程ROM |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 529K |
| 代理商： | BR34L02FV-W |
BR34L02FV-W
Memory ICs
z
Application
1) WP effective timing
WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to
WP effective timing
as follows.
During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective
period.
The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data
for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of
the SCL which takes in D0 must be more than 100ns.
The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (t
WR
) is the cancellation
effective period. In case of setting WP to “H” during t
WR
, WRITE operation is stopped in the middle and the data of
accessing address is not guaranteed, so that write correct data again please.
It is not necessary waiting t
WR
(5msmax.) after stopping command by WP, because the device is stand by state.
Rev.A
13/24
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
DATA
D7
D6
D5
D4
D3
D2
D1
D0
SDA
WP
tWR
WP cancellation invalid period
WP cancellation effective period
No data will be written
Stop of the write
operation
Data is not
guaranteed
SCL
SDA
D1
D0
ACK
AN ENLARGEMENT
· The rising edge of the clock
which take in D0
SCL
SDA
D0
ACK
AN ENLARGEMENT
· The rising edge
of SDA
Fig.18 WP EFFECTIVE TIMING
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