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參數(shù)資料
| 型號： | BR24L04F-W |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 512】8 bit electrically erasable PROM |
| 中文描述： | 512】8位電可擦除可編程ROM |
| 文件頁數(shù)： | 17/25頁 |
| 文件大小： | 388K |
| 代理商： | BR24L04F-W |
BR24L04-W / BR24L04F-W / BR24L04FJ-W
Memory ICs
BR24L04FV-W / BR24L04FVM-W
5) Notes for power supply
V
CC
rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device
may not work properly due to an incomplete reset of internal circuit.
To prevent this, the device has the feature of P.O.R. and LV
CC
.
In the case of power up, keep the following conditions to ensure functions of P.O.R and LV
CC
.
(1) It is necessary to be “SDA
=
‘H’ ” and “SCL
=
’L’ or ‘H’ ”.
(2) Follow the recommended conditions of t
R
, t
OFF
, Vbot for the function of P.O.R. durning power up.
t
R
17/25
t
OFF
Vbot
V
CC
rising wave from
V
CC
0
Recommended conditions of t
R
, t
OFF
, Vbot
Below 10ms
Below 100ms
t
R
t
OFF
Vbot
Below 0.3V
Below 0.2V
Above 10ms
Above 10ms
(3) Prevent SDA and SCL from being “Hi-Z”.
In case that condition 1. and / or 2. cannot be met, take following actions.
A) Unable to keep condition 1. (SDA is “LOW” during power up.)
→
Control SDA, SCL to be “HIGH” as figure below.
t
LOW
t
DH
t
SU:DAT
After V
CC
becomes stable
SDA
SCL
V
CC
a) SCL
=
"H" and SDA
=
"L"
t
SU:DAT
After V
CC
becomes stable
b) SCL
=
"L" and SDA
=
"L"
B) Unable to keep condition 2.
→
After power becomes stable, execute software reset. (See Page14 )
C) Unable to keep condition 1 and 2.
→
Follow the instruction A first, then the instruction B.
LV
CC
circuit
LV
CC
circuit inhibit write operation at low voltage, and prevent an inadvertent write. Below the LV
CC
voltage
(Typ.
=
1.2V), write operation is inhibited.
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| BR24L04FJ-W | 512】8 bit electrically erasable PROM |
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| BR24L04FVM-W | 512】8 bit electrically erasable PROM |
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