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參數(shù)資料
| 型號： | bq2202 |
| 廠商： | Benchmark Technology Group |
| 英文描述： | SRAM Nonvolatile Controller With Reset(靜態(tài)RAM非易失性控制器單元(帶復位）) |
| 中文描述： | 非易失控制器的SRAM（靜態(tài)RAM的非易失性控制器單元（帶復位）帶復位） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 83K |
| 代理商： | BQ2202 |
If a secondary cell is not to be used, the BC
S
pin must be
tied directly to V
SS
. If both inputs are used, during
power failure the V
OUT
and CE
CON
outputs are forced
high by the secondary cell so long as it is greater than
2.5V. Only the secondary cell is loaded by the data reten-
tion current of the SRAM until the voltage at the BC
S
pin falls below 2.5V. When and if the voltage at BC
S
falls below 2.5V, an internal isolation switch automati-
cally transfers the load from the secondary cell to the
primary cell.
To prevent battery drain when there is no valid data to
retain, V
OUT
, CE
CON1
, and CE
CON2
are internally iso-
lated from BC
P
and BC
S
by either:
I
Initial connection of a battery toBC
P
or BC
S
or
I
Presentation of an isolation signal on CE.
A valid isolation signal requires CE low as V
CC
crosses
both V
PFD
and V
SO
during a power-down. See Figure
2.
Between these two points in time, CE must be
brought to V
CC
(0.48 to 0.52) and held for at least
700ns. The isolation signal is invalid if CE exceeds V
CC
*
0.54 at any point between V
CC
crossing V
PFD
and V
SO
.
T he battery is connected to V
OUT
, CE
CON1
, and
CE
CON2
immediately on subsequent application and
removal of V
CC
.
3
TD220201.eps
VCC
CE
VPFD
VSO
0.5 VCC
700ns
Figure 2. Battery Isolation Signal
Truth Table
Input
Output
CE
A
CE
CON1
CE
CON2
H
X
H
H
L
L
L
H
L
H
H
L
Sept. 1997 D
bq2202
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