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參數(shù)資料
| 型號： | bq2202 |
| 廠商： | Benchmark Technology Group |
| 英文描述： | SRAM Nonvolatile Controller With Reset(靜態(tài)RAM非易失性控制器單元(帶復(fù)位）) |
| 中文描述： | 非易失控制器的SRAM（靜態(tài)RAM的非易失性控制器單元（帶復(fù)位）帶復(fù)位） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 83K |
| 代理商： | BQ2202 |
As the supply continues to fall past V
PFD
, an internal
switching device forces V
OUT
to the internal backup en-
ergy source. CE
CON1
and CE
CON2
are held high by the
V
OUT
energy source.
During power-up, V
OUT
is switched back to the 5V sup-
ply as V
CC
rises above the backup cell input voltage
sourcing V
OUT
. Outputs CE
CON1
and CE
CON2
are held
inactive for time t
CE R
(120ms maximum) after the
power supply has reached V
PFD
, independent of the CE
input, toallow for processor stabilization.
During power-valid operation, the CE input is passed
through to one of the two CE
CON
outputs with a propa-
gation delay of less than 10ns. The CE input is output on
one of the two CE
CON
output pins; depending on the
level of bank select input A, as shown in the Truth Ta-
ble.
Bank select input A is usually tied to a high-order ad-
dress pin so that a large nonvolatile memory can be de-
signed using lower-density memory devices. Nonvolatility
and decoding are achieved by hardware hookup as shown
in Figure1.
The reset output (RST) goes active within t
PFD
(150
μ
sec
maximum) after V
PFD,
and remains active for a minimum
of 40ms (120ms maximum) after power returns valid. The
RST output can be used as the power-on reset for a micro-
processor. Access to the external RAM may begin when
RST returns inactive.
Energy Cell Inputs—BC
P
,BC
S
Two backup energy source inputs are provided on the
bq2202—a primary cell BC
P
and a secondary cell BC
S
.
The primary cell input is designed to accept any 3V pri-
mary battery (non-rechargeable), typically some type of
lithium chemistry. If a primary cell is not to be used, the
BC
P
pin should be grounded. The secondary cell input
BC
S
is designed to accept constant-voltage current-
limited rechargeablecells.
During normal 5V power valid operation, 3.3V is output
on theBC
S
pin and is current-limited internally.
2
FG220201.eps
VCC
CE
BCP
THS
VSS
VOUT
bq2202
VCC
CE
CMOS
SRAM
5V
From Address
Decoder
CECON2
BCS
RST
CECON1
A
VCC
CE
CMOS
SRAM
To Microprocessor
Figure 1. Hardware Hookup (5% Supply Operation)
Sept. 1997 D
bq2202
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BQ2202PN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SRAM NV Controller With Reset |
| BQ2202PNN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SRAM NV Controller With Reset |
| BQ2202PN-N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| BQ2202SN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| BQ2202SNN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SRAM NV Controller With Reset |
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